DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 9 and 16.
b. Pending: 1-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KEDIA PG PUB 20210240566 (hereinafter Kedia).
Regarding independent claim 1, Kedia teaches an assembly (figure 1 of Kedia, 300 in figure 3 of Kedia), comprising:
a first memory channel interface (wide memory channel #1 interface 131 in figure 1A/figure 3 of Kedia, [0014] of Kedia, “…wide memory channel #1 interface 131…”) comprising a first command/address (CA) interface (memory access interfaces 311a, 312b in figure 3 of Kedia), a first lower data byte interface (memory -access interface 322a/322b associated with memory component 322 in figure 3 of Kedia, [0011] of Kedia, “…data signal lines of these pairs are routed to the controller separately such that each memory component of the pair, when so configured, supplies one-half (½) of the data width of the memory channel (e.g., for a 16-bit memory channel, each component of the pair supplies 8 bits.)…”), and a first upper data byte interface (memory -access interface 321a/321b associated with memory component 321 in figure 3 of Kedia);
a second memory channel interface (wide memory channel #2 in figure 1A/figure 3 of Kedia, [0014] of Kedia, “…wide memory channel #2 interface 132…”) comprising a second CA interface (313a/314b in figure 3 of Kedia), a second lower data byte interface (memory -access interface 324a/324b associated with memory component 324 in figure 3 of Kedia), and a second upper data byte interface (memory -access interface 323a/323b associated with memory component 323 in figure 3 of Kedia);
a first two memory integrated circuits (memory components 321/322 in figure 3 of Kedia) electrically coupled to the first CA interface (memory access interfaces 311a, 312b in figure 3 of Kedia) and being stacked with (paired and affixed to opposite of substrate/PCB, [0011] of Kedia, “…pairs of these memory components may be affixed to opposite sides of a substrate (e.g., printed circuit board) and receive the same command/address signal lines from each of the memory channels…”, the claim merely recites “being stacked with” and does not require direct die-on-die attachment or absence of an intervening substrate. Under BRI, integrated circuits arranged on opposite sides of a common substrate in a paired vertical configuration are considered stacked) a second two memory integrated circuits (memory components 323/324 in figure 3 of Kedia), the second two memory integrated circuits (memory components 323/324 in figure 3 of Kedia) electrically coupled to the second CA interface (313a/314b in figure 3 of Kedia);
the first two memory integrated circuits (memory components 321/322 in figure 3 of Kedia) configurable to use different ones of the first lower data byte interface (memory -access interface 322a/322b associated with memory component 322 in figure 3 of Kedia) and the first upper data byte interface (memory -access interface 321a/321b associated with memory component 321 in figure 3 of Kedia);
the second two memory integrated circuits (memory components 323/324 in figure 3 of Kedia) configurable to use different ones of the second lower data byte interface (memory -access interface 324a/324b associated with memory component 324 in figure 3 of Kedia) and the second upper data byte interface (memory -access interface 323a/323b associated with memory component 323 in figure 3 of Kedia); and
a third memory integrated circuit (325 in figure 3 of Kedia), electrically coupled to the first CA interface (wide memory channel #1 interface 131 in figure 1A/figure 3 of Kedia, [0014] of Kedia, “…wide memory channel #1 interface 131…”) and the second CA interface (wide memory channel #2 in figure 1A/figure 3 of Kedia, [0014] of Kedia, “…wide memory channel #2 interface 132…”), and being stacked with the first two memory integrated circuits (memory components 321/322 in figure 3 of Kedia) and the second two memory integrated circuits (memory components 323/324 in figure 3 of Kedia), a lower data byte interface (325a in figure 3 of Kedia) of the third memory integrated circuit electrically coupled to the first lower data byte interface (memory -access interface 322a/322b associated with memory component 322 in figure 3 of Kedia), an upper data byte interface (325b in figure 3 of Kedia) of the third memory integrated circuit electrically coupled to the second lower data byte interface (memory -access interface 324a/324b associated with memory component 324 in figure 3 of Kedia).
Regarding claim 2, Kedia teaches the assembly of claim 1, wherein the first CA interface (memory access interfaces 311a, 312b in figure 3 of Kedia) and the second CA interface (313a/314b in figure 3 of Kedia) are time multiplexed (interpreted as “share at least one common signal, such as a clock and/or strobe signals during access cycle) on a same set of physical connections (figure 3, [0037]-[0039], “…the memory access interfaces 321a-325a and 321b-325b on a respective memory component 321-325 may share at least one common signal, such as a clock and/or strobe signal(s)…Memory access interfaces 311a, 312b, and 315a are effectively operated in ‘lockstep’ (i.e., receiving the same command and address information for what is effectively the same access cycles) to form wide memory channel #1 interface. Memory access interfaces 315b, 313a, and 314b are effectively operated in lockstep to form wide memory channel #2 interface…Memory components 321, 322, 323, and 324 (i.e., not memory component 325) may be paired. When paired, memory components 321, 322, 323, and 324 may be affixed to opposite sides of a substrate (e.g., printed circuit board). These pairs are operatively coupled (e.g., connected) to receive the same command/address signal lines from controller 310…”)
Regarding claim 3, Kedia teaches the assembly of claim 1, wherein a first one (321 in figure 3) of the first two memory integrated circuits (memory components 321/322 in figure 3 of Kedia) is to, in response a first CA command (CA command to channel #1, data transfer function), communicate a first data burst (channel #1 32-bit data burst, via 311a) via the first lower data byte interface (memory -access interface 322a/322b associated with memory component 322 in figure 3 of Kedia) and a second one (322 in figure 3) of the first two memory integrated circuits (memory components 321/322 in figure 3 of Kedia) is to, in response to the first CA command (CA command to channel #1, data transfer), communicate a second data burst (channel #1 32-bit data burst, via 312b) via the first upper data byte interface (memory -access interface 321a/321b associated with memory component 321 in figure 3 of Kedia), wherein the first data burst and the second data burst are communicated concurrently (figure 3, [0011], [0037]-[0041], “…data signal lines of these pairs are routed to the controller separately such that each memory component of the pair, when so configured, supplies one-half (1/2) of the data width of the memory channel (e.g., for a 16-bit memory channel, each component of the pair supplies 8 bits). Configuring the pair to operate in this manner is known as ‘clamshell’ mode…Memory access interfaces 321a-325a and 321b-325b for a given memory component 321-325 are independent in that they can operate independently of each other to provide command, address, and data transfer functions to the respective memory access channel that they are operatively coupled to…Memory access interfaces 311a, 312b, and 315a are effectively operated in ‘lockstep’ (i.e., receiving the same command and address information for what is effectively the same access cycles) to form wide memory channel #1 interface…Memory component 321 is also connected to, via memory access interface 321b, to the same command/address signal lines of controller 310 (and thus connected to memory access interface 312b as memory component 322 is connected to, via memory access interface 322b…two independent 39 or 40-bit channels (i.e., 32-bits of data and 7-bits of error correction code or 32-bits of data and 8-bits of error correction code) may be provided using just five (5) memory components. Two memory components 321 and 322 on wide memory channel #1 interface provide 32-bits of data and one-half (½) of memory component 325 provides either 7 or 8 bits (depending upon a desired configuration and/or ECC coding scheme) of error correcting code data for a total of either 39 or 40-bits, respectively. Likewise, two memory components 323 and 324 on wide memory channel #2 interface provide 32-bits of data and one-half (½) of memory component 325 provides either 7 or 8 bits (depending upon a desired configuration and/or ECC coding scheme) of error correcting code data for a total of either 39 or 40-bits, respectively…”)
Regarding claim 4, Kedia teaches the assembly of claim 3, wherein the third memory integrated circuit (325 in figure 3) is to, in response to the first CA command (CA command to channel #1, data transfer), communicate a third data burst (8-bit ECC data burst, figure 3, [0040]-[0041]) after a one of the first data burst (channel #1 32-bit data burst, via 311a) and the second data burst (channel #1 32-bit data burst, via 312b).
Regarding claim 5, Kedia teaches the assembly of claim 1, wherein a first one (321 in figure 3) of the first two memory integrated circuits (memory components 321/322 in figure 3 of Kedia) is to, in response a first CA command (CA command to channel #1, data transfer function), communicate a first portion of a first data burst (channel #1 32-bit data burst, first bits of first set of check bits) via the first lower data byte interface (memory -access interface 322a/322b associated with memory component 322 in figure 3 of Kedia) and a second portion of the first data burst (channel #1 32-bit data burst, second bits of first set of check bits) via the first upper data byte interface (memory -access interface 321a/321b associated with memory component 321 in figure 3 of Kedia) and a second one (322 in figure 3) of the first two memory integrated circuits (memory components 321/322 in figure 3 of Kedia) is to, in response to the first CA command (CA command to channel #1, data transfer function), communicate a second data burst (channel #1 32-bit data burst, via 312b) via the first upper data byte interface (memory -access interface 321a/321b associated with memory component 321 in figure 3 of Kedia), wherein the first portion of the first data burst (channel #1 32-bit data burst, first bits of first set of check bits) and a first portion of the second data burst (channel #1 32-bit data burst, first bits of second set of check bits) are communicated concurrently (figure 3, [0040]-[0041], Kedia paired device or clamshell arrangement divides the data width among paired memory components operating in parallel).
Regarding claim 6, Kedia teaches the assembly of claim 5, wherein the third memory integrated circuit (325 in figure 3, [0040]-[0041]) is to, in response to the first CA command (CA command to channel #1, data transfer function), communicate a third data burst (8-bit ECC data burst, ECC1) after the first portion of the first data burst (channel #1 32-bit data burst, first bits of first set of check bits).
Regarding claim 7, Kedia teaches the assembly of claim 1, wherein, during a read data burst (access data burst) performed in response to a read command (e.g., access command) communicated via the first CA interface (memory access interfaces 311a, 312b in figure 3 of Kedia), the third memory integrated circuit (325 in figure 3) is to transmit a read data strobe signal (common clock/strobe signal) to the first two memory integrated circuits (figure 3, [0037]-[0041]).
Regarding claim 8, Kedia teaches the assembly of claim 7, wherein, during the read data burst, the first two memory integrated circuits are to not transmit read data strobe signals (figure 3, [0037]-[0041], Keida teaches the paired memory components operating in clamshell or lockstep mode using the common strobe or timing signal, such that the first two memory components need not independently transmit separate read-data-strobe signals during the burst).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-13, 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over KEDIA PG PUB 20210240566 (hereinafter Kedia), in view of Giduturi PG PUB 20230335176 (hereinafter Giduturi).
Regarding independent claim 9, Kedia teaches an integrated circuit stack (figure 1 of Kedia, 300 in figure 3 of Kedia), comprising:
a first external command/address (CA) interface (wide memory channel #1 interface 311a/312b/315a in figure 3 of Kedia) to receive commands and addresses from a device external to the integrated circuit stack;
a second external CA interface (wide memory channel #2 interface 132 in figure 1A, implemented as 313a/314b/315b in figure 3 of Kedia) to receive commands and addresses from the device external to the integrated circuit stack;
a first data interface (interface associated with 321, e.g., 321a in figure 3 of Kedia) to communicate data with the device external to the integrated circuit stack in response to commands and addresses received via the first external CA interface (wide memory channel #1 interface 131 in figure 1A, implemented as 311a/312b/315a in figure 3 of Kedia);
a second data interface (interface associated with 322, e.g., 322b in figure 3 of Kedia) to communicate data with the device external to the integrated circuit stack in response to commands and addresses received via the first external CA interface (wide memory channel #1 interface 131 in figure 1A, implemented as 311a/312b/315a in figure 3 of Kedia);
a third data interface (interface associated with component 323, e.g., 323a in figure 3) to communicate data with the device external to the integrated circuit stack in response to commands and addresses received via the second external CA interface (wide memory channel #2 interface 132 in figure 1A, implemented as 313a/314b/315b in figure 3 of Kedia);
a fourth data interface (interface associated with component 324, e.g., 324b in figure 3) to communicate data with the device external to the integrated circuit stack in response to commands and addresses received via the second external CA interface (wide memory channel #2 interface 132 in figure 1A, implemented as 313a/314b/315b in figure 3 of Kedia);
a first memory device (321 in figure 3 of Kedia) comprising at least a first memory array, the first memory device to receive commands and addresses via the first external CA interface (wide memory channel #1 interface 131 in figure 1A, implemented as 311a/312b/315a in figure 3 of Kedia), the first memory device configurable to communicate data via the first data interface (interface associated with 321, e.g., 321a in figure 3 of Kedia);
a second memory device (322 in figure 3 of Kedia) comprising at least a second memory array, the second memory device to receive commands and addresses via the first external CA interface (wide memory channel #1 interface 131 in figure 1A, implemented as 311a/312b/315a in figure 3 of Kedia), the second memory device (322 in figure 3 of Kedia)configurable to communicate data via the second data interface (interface associated with 322, e.g., 322b in figure 3);
a third memory device (323 in figure 3 of Kedia) comprising at least a third memory array, the third memory device to receive commands and addresses via the second external CA interface (wide memory channel #2 interface 132 in figure 1A, implemented as 313a/314b/315b in figure 3 of Kedia), the third memory device configurable to communicate data via the third data interface (interface associated with component 323, e.g., 323a in figure 3);
a fourth memory device (324 in figure 3 of Kedia) comprising at least a fourth memory array, the fourth memory device to receive commands and addresses via the second external CA interface (wide memory channel #2 interface 132 in figure 1A, implemented as 313a/314b/315b in figure 3 of Kedia), the fourth memory device configurable to communicate data via the fourth data interface (interface associated with component 324, e.g., 324b in figure 3); and
a fifth memory device (325 in figure 3 of Kedia) comprising at least a fifth memory array, the fifth memory device to receive commands and addresses via the first external CA interface (wide memory channel #1 interface 131 in figure 1A, implemented as 311a/312b/315a in figure 3 of Kedia) and the second external CA interface (wide memory channel #2 interface 313a/314b/315b in figure 3 of Kedia), the fifth memory device (325 in figure 3 of Kedia) to, in response to commands received via the first external CA interface (wide memory channel #1 interface 131 in figure 1A, implemented as 311a/312b/315a in figure 3 of Kedia), communicate data (525 has independent interfaces 325a/325b, one for each wide memory channel) via the first data interface (interface associated with 321, e.g., 321a in figure 3 of Kedia), the fifth memory device (325 in figure 3 of Kedia) to, in response to commands received via the second external CA interface (wide memory channel #2 interface 313a/314b/315b in figure 3 of Kedia), communicate data (325 also independently supplies ECC/check-bit information to both wide channels) via the third data interface (interface associated with component 323, e.g., 323a in figure 3).
Kedia does not provide details on circuit stacks.
Giduturi teaches a packaged memory device having multiple memory dies stacked together, with a primary die and multiple secondary dies coupes through intra-package connects (see figure 2-5 of Giduturi).
It would have been obvious to implement Kedia’s five memory components as the dies of Giduturi’s integrated -circuit stack.
Regarding claim 10, the combination of Kedia and Giduturi teaches the integrated circuit stack of claim 9, wherein the first external CA interface (wide memory channel #1 interface 131 in figure 1A, implemented as 311a/312b/315a in figure 3 of Kedia) and the second external CA interface (wide memory channel #2 interface 132 in figure 1A, implemented as 313a/314b/315b in figure 3 of Kedia) are time multiplexed on a same set of physical connections (figure 3, [0037]-[0039], “…the memory access interfaces 321a-325a and 321b-325b on a respective memory component 321-325 may share at least one common signal, such as a clock and/or strobe signal(s)…Memory access interfaces 311a, 312b, and 315a are effectively operated in ‘lockstep’ (i.e., receiving the same command and address information for what is effectively the same access cycles) to form wide memory channel #1 interface. Memory access interfaces 315b, 313a, and 314b are effectively operated in lockstep to form wide memory channel #2 interface…Memory components 321, 322, 323, and 324 (i.e., not memory component 325) may be paired. When paired, memory components 321, 322, 323, and 324 may be affixed to opposite sides of a substrate (e.g., printed circuit board). These pairs are operatively coupled (e.g., connected) to receive the same command/address signal lines from controller 310…”)
Regarding claim 11, the combination of Kedia and Giduturi teaches the integrated circuit stack of claim 9, wherein the first memory device (321 in figure 3 of Kedia) is to, in response a first CA command (CA command to channel #1, data transfer) received via the first external CA interface (wide memory channel #1 interface 131 in figure 1A, implemented as 311a/312b/315a in figure 3 of Kedia), communicate a first data burst (channel #1 32-bit data burst, via 311a) via the first data interface (interface associated with 321, e.g., 321a in figure 3 of Kedia) and the second memory device (322 in figure 3 of Kedia) is to, in response to the first CA command (CA command to channel #1, data transfer), communicate a second data burst (channel #1 32-bit data burst, via 312b) via the second data interface (interface associated with 322, e.g., 322b in figure 3), wherein the first data burst (channel #1 32-bit data burst, via 311a) and the second data burst (channel #1 32-bit data burst, via 312b) are communicated concurrently (figure 3, [0040]-[0041], Kedia paired device or clamshell arrangement divides the data width among paired memory components operating in parallel).
Regarding claim 12, the combination of Kedia and Giduturi teaches the integrated circuit stack of claim 11, wherein the third memory device is to, in response to the first CA command, communicate a third data burst on the first data interface after the first data burst is complete (Kedia teaches independently accessing the respective memory components and communicating data burst through the memory interfaces. Claim does not require that the first data burst and the third data burst be responsive to the same command. Accordingly, after completion of a first data burst from the first meory device, a subsequent command causing the third memory device to communicate a third data burst via the first data interface satisfies the claimed sequence).
Regarding claim 13, the combination of Kedia and Giduturi teaches the integrated circuit stack of claim 9, wherein the first memory device (321 in figure 3 of Kedia) is to, in response a first CA command (CA command to channel #1, data transfer) received via the first external CA interface (wide memory channel #1 interface 131 in figure 1A, implemented as 311a/312b/315a in figure 3 of Kedia), communicate a first subset of a first data burst (channel #1 32-bit data burst, via 311a) via the first data interface (interface associated with 321, e.g., 321a in figure 3 of Kedia) and the second memory device (322 in figure 3 of Kedia) is to, in response to the first CA command, communicate a second data burst (channel #1 32-bit data burst, via 312b) via the second data interface (interface associated with 322, e.g., 322b in figure 3), wherein the first subset of the first data burst and a second subset of the second data burst (channel #1 32-bit data burst, via 312b) are communicated concurrently.
Regarding claim 15, the combination of Kedia and Giduturi teaches the integrated circuit stack of claim 9, wherein, during a read data burst (access data burst) performed in response to a read command (e.g., access command) communicated via the first CA interface (memory access interfaces 311a, 312b in figure 3 of Kedia), the third memory device (323 in figure 3 of Kedia) is to transmit a read data strobe signal to the first memory device and the second memory device.
Regarding independent claim 16, the combination of Kedia and Giduturi teaches a method of operating an integrated circuit stack (figures 2-5 of Giduturi), comprising:
receiving, via a first external command/address (CA) interface (wide memory channel #1 interface 311a/312b/315a in figure 3 of Kedia), a first command from a device external (any device not part of integrated circuit, e.g., controller, host), to the integrated circuit stack;
receiving, via a second external CA interface (wide memory channel #2 interface 132 in figure 1A, implemented as 313a/314b/315b in figure 3 of Kedia), a second command from the device external (any device not part of integrated circuit, e.g., controller, host, controller 310 in figure 3 of Kedia, which is external to the memory components 321-325 constituting the integrated circuit stack) to the integrated circuit stack;
in response to the first command (access command through channel #1 in figure 3 of Kedia), communicating, via a first data interface (interface associated with 321, e.g., 321a in figure 3 of Kedia) and by a first memory device (321 in figure 3 of Kedia) in the integrated circuit stack, first data (“B0” read data from 321 in figure 3 of Kedia) with the device external to the integrated circuit stack;
in response to the first command (access command through channel #1 in figure 3 of Kedia), communicating, via a second data interface (interface associated with 322, e.g., 322b in figure 3 of Kedia) and by a second memory device (322 in figure 3 of Kedia) in the integrated circuit stack, second data (“B3” read data from 322 in figure 3 of Kedia) with the device external to the integrated circuit stack;
in response to the second command (access command through channel #2 in figure 3 of Kedia), communicating, via a third data interface (interface associated with component 323, e.g., 323a in figure 3) and by a third memory device (323 in figure 3 of Kedia) in the integrated circuit stack, third data (“B0” read data from 323 in figure 3 of Kedia) with the device external to the integrated circuit stack;
in response to the second command (access command through channel #2 in figure 3 of Kedia), communicating, via a fourth data interface (interface associated with component 324, e.g., 324b in figure 3) and by a fourth memory device (324 in figure 3 of Kedia) in the integrated circuit stack, fourth data (“B3” read data from 324 in figure 3 of Kedia) with the device external to the integrated circuit stack;
in response to the first command (access command through channel #1 in figure 3 of Kedia), communicating, via the first data interface (interface associated with 321, e.g., 321a in figure 3 of Kedia) and by a fifth memory device (325 in figure 3 of Kedia) in the integrated circuit stack, fifth data (EC1 in figure 3 of Kedia) with the device external to the integrated circuit stack; and
in response to the second command (access command through channel #2 in figure 3 of Kedia), communicating, via the third data interface and by the fifth memory device (325 in figure 3 of Kedia) in the integrated circuit stack, sixth data (EC2 in figure 3 of Kedia) with the device external to the integrated circuit stack.
Regarding claim 17, the combination of Kedia and Giduturi teaches the method of claim 16, wherein the first data (“B0” read data from 321 in figure 3 of Kedia) and the second data (“B3” read data from 322 in figure 3 of Kedia) are communicated concurrently.
Regarding claim 18, the combination of Kedia and Giduturi teaches the method of claim 16, wherein after the fifth data burst is communicated via the first data interface (interface associated with 321, e.g., 321a in figure 3 of Kedia) after the first data (“B0” read data from 321 in figure 3 of Kedia) has been communicated via the first data interface (interface associated with 321, e.g., 321a in figure 3 of Kedia) .
Regarding claim 19, the combination of Kedia and Giduturi teaches the method of claim 16, further comprising: storing, in the fifth memory device, at least one check symbol (EC1 or EC2 in figure 3 of Kedia).
Allowable Subject Matter
Claims 14, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is KEDIA PG PUB 20210240566 (hereinafter Kedia).
KEDIA discloses multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.
Regarding claim 14, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the third memory device is to, in response to the first CA command, communicate a third data burst via the first data interface after the first subset of the first data burst.
Regarding claim 20, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: detecting an error on the first data interface associated with the first memory device; and configuring the first memory device to not use the first data interface.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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