DETAILED ACTION
1. Claims 1-16 and 18-21 are pending in this application filed on January 15, 2025.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
3. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
4. Claims 3, 13, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claims require reception of preamble signals of the first and second data bursts from a first and second data paths during “the preamble interval.” “The preamble interval” claimed is the preamble interval of the preamble of the first data burst. The specification does not disclose receiving a second preamble signal of the second data burst during the preamble interval of the first data burst through a different path as recite in the claims.
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 3, 6, 7, 9, and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
7. Claims 3 and 13 recite the limitation “data receive circuitry is to receive.” It is not clear whether this is meant to be a functional limitation or an intended method step to be performed by the data receive circuitry. It is also not clear which, if any, of the claimed structure performs the function or the step of combining to form a pseudo-differential signal during the preamble interval.
8. Claim 6 recites the limitation “an internal strobe signal adjusted based on the edge error information.” It is not clear whether this is functional limitation or a method step performed by one of the structures. It is also not clear which of the claimed structures performed this step.
9. Claim 7 recites the limitation “the edge sampling circuitry defines a clock phase adjustment paths; the valid portion of the first data burst is sampled in a data sampling path that is separate from the clock path adjustment path” It is not clear what it means for the edge sampling circuitry to define a clock phase adjustment path or how a circuitry defines a path. It is also not clear whether the limitation “the valid portion of the data bust is sampled in a data sampling path” is meant to be functional limitation or an action that is taken by the edge sampling circuitry.
10. Claim 9 recites “the lock-loop circuit exhibits a frequency that is locked to the clock signal, and phase that is locked to the data reception timing.” It is not clear what it means for a circuit to exhibit a frequency or a phase.
11. The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
12. Claims 2-3 and 12-13 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claims describe data signals received or to be received by the claimed memory chip, but fails to further limit the structure or the functions of the claimed integrated memory chip. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
13. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. Claims 1-2, 4-5, 8-12, 14-16, 18-19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US Pat. No. US 9,881,662 (“Giovannini”) in view of US Pat. No. US 9,213,657 (“Zerbe”).
15. With respect to claim 1, Giovannini discloses an integrated circuit (IC) memory chip, comprising:
clock receive circuitry to receive a clock signal (see Abstract);
command/address (C/A) receive circuitry to time reception of C/A signals using the clock signal (see Abstract ; this is inherent in any functional memory system);
data receive circuitry to receive a first data burst from a first data path (Abstract);
calibration circuitry to set an initial sampling phase for data reception timing of the first data burst relative to the clock signal (see FIGs. 3-7 and 12); and
[timing circuitry to track drift in the data reception timing using phase information from at least one toggling edge of the first data burst and to adjust the data reception timing based on the phase information].
However, Giovannini does not specifically disclose a timing circuitry to track drift in the data reception timing (limitation above in square brackets). On the other hand, Zerbe discloses an integrated circuit (IC) memory chip (12:18-21) comprising timing circuitry to track drift in the data reception timing using phase information from at least one toggling edge of the first data burst and to adjust the data reception timing based on the phase information (see Abstract and FIG. 1A, Edge Tracking Circuit 108 and PLL Circuit 106).
It would have been obvious to one of ordinary skill in the art to adopt Zerbe’s timing drift compensation teachings in the memory system of Giovannini in order to support rank switching.
16. With respect to claims 11 and 18, see the rejection of claim 1 above.
17. With respect to claim 2, Giovannini and Zerbe disclose the IC memory chip of claim 1, wherein: the first data burst includes a preamble having a preamble interval; and wherein the phase information is associated with at least one toggling edge of the preamble (Zerbe, Abstract; see also 4:21-25).
18. With respect to claim 4, Giovannini and Zerbe disclose the IC memory chip of claim 2, further comprising: mode register storage to store a value representing a duration and a pattern of the preamble interval (Zerbe, 5:42-50).
19. With respect to claim 5, Giovannini and Zerbe disclose the IC memory chip of claim 1, wherein: the timing circuitry includes an oversampling circuit to track the drift in the data reception timing (Zerbe, 5:57-6:3).
20. With respect to claim 8, Giovannini and Zerbe disclose the IC memory chip of claim 1, wherein: the timing circuitry includes a locked-loop circuit to track the drift in the data reception timing (Zerbe, FIG. 1A, PLL Circuit 108).
21. With respect to claim 9, Giovannini and Zerbe disclose the IC memory chip of claim 8, wherein: the locked-loop circuit exhibits a frequency that is locked to the clock signal, and a phase that is locked to the data reception timing (Zerbe, 2:67-3:4).
22. With respect to claim 10, Giovannini and Zerbe disclose the IC memory chip of claim 1, embodied as an IC dynamic random access memory (DRAM) chip (Giovannini, FIG. 2; Zerbe, 2:61-63).
23. With respect to claims 12 and 19, see the rejection of claim 2 above.
24. With respect to claims 14 and 21, see the rejection of claim 4 above.
25. With respect to claim 15, Giovannini and Zerbe disclose the DRAM device of claim 11, further comprising: transmit circuitry to transmit feedback to a memory controller during the first training, the feedback indicating a relative alignment between the first data pattern and the internally-generated strobe signal; and wherein the initial sampling phase is set based on the feedback (Giovannini, FIG. 12).
26. With respect to claim 16, see the rejection of claim 5 above.
Conclusion
27. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571)272-4179. The examiner can normally be reached 9 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on (571) 272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Woo H Choi/
Primary Examiner,
Art Unit 3992
1. An integrated circuit (IC) memory chip, comprising:
clock receive circuitry to receive a clock signal;
command/address (C/A) receive circuitry to time reception of C/A signals using the clock signal;
data receive circuitry to receive a first data burst from a first data path;
calibration circuitry to set an initial sampling phase for data reception timing of the first data burst relative to the clock signal; and
timing circuitry to track drift in the data reception timing using phase information from at least one toggling edge of the first data burst and to adjust the data reception timing based on the phase information.
2. The IC memory chip of claim 1, wherein: the first data burst includes a preamble having a preamble interval; and wherein the phase information is associated with at least one toggling edge of the preamble.
3. The IC memory chip of claim 2,
wherein: the data receive circuitry is to receive a second data burst from a second data path;
wherein during the preamble interval, the data receive circuitry is to receive a first single-ended preamble signal of the first data burst from the first data path and a second single-ended preamble signal of a second data burst from the second data path; and
wherein the first single-ended preamble signal and the second single-ended preamble signal are combined to form a pseudo-differential signal during the preamble interval.
4. The IC memory chip of claim 2, further comprising: mode register storage to store a value representing a duration and a pattern of the preamble interval.
5. The IC memory chip of claim 1, wherein: the timing circuitry includes an oversampling circuit to track the drift in the data reception timing.
6. The IC memory chip of claim 5, wherein the oversampling circuit comprises:
edge sampling circuitry to sample the at least one toggling edge of the first data burst to generate multiple edge samples that reflect edge error information; and
an internal strobe generation circuit to generate an internal strobe signal based on the clock signal to sample a valid portion of the first data burst, the internal strobe signal adjusted based on the edge error information.
7. The IC memory chip of claim 6, wherein: the edge sampling circuitry defines a clock phase adjustment path; the valid portion of the first data burst is sampled in a data sampling path that is separate from the clock phase adjustment path; and wherein the memory IC chip further includes decision-feedback equalization (DFE) circuitry disposed in the data sampling path to correct for inter-symbol interference.
8. The IC memory chip of claim 1, wherein: the timing circuitry includes a locked-loop circuit to track the drift in the data reception timing.
9. The IC memory chip of claim 8, wherein: the locked-loop circuit exhibits a frequency that is locked to the clock signal, and a phase that is locked to the data reception timing.
10. The IC memory chip of claim 1, embodied as an IC dynamic random access memory (DRAM) chip.
11. A dynamic random access memory (DRAM) device, comprising:
clock receive circuitry to receive a clock signal;
command/address (C/A) receive circuitry to time reception of C/A signals using the clock signal; and
calibration circuitry to train timing of an internally-generated strobe signal to the clock signal, the calibration circuitry to perform a first training for setting an initial sampling phase for the internally-generated strobe signal, the first training to train data reception timing of a first data pattern relative to the clock signal; and perform a second sampling training to determine a second sampling phase adjustment to the initial sampling phase, the second sampling phase adjustment determined using phase information from at least one toggling edge of a first data burst and to adjust the data reception timing based on the phase information.
14. The DRAM device of claim 12, further comprising: mode register storage to store a value representing a duration and a pattern of the preamble interval.
15. The DRAM device of claim 11, further comprising: transmit circuitry to transmit feedback to a memory controller during the first training, the feedback indicating a relative alignment between the first data pattern and the internally-generated strobe signal; and wherein the initial sampling phase is set based on the feedback.
16. The DRAM device of claim 11, further comprising: an oversampling circuit to perform the second sampling training.
17. (canceled)
18. A method of operating a dynamic random access memory (DRAM) device, comprising:
receiving a clock signal;
timing reception of command/address (C/A) signals using the clock signal; and
training timing of an internally-generated strobe signal to the clock signal, the training including:
performing a first training for setting an initial sampling phase for the internally-generated strobe signal, the first training to train data reception timing of a first data pattern relative to the clock signal; and
performing a second sampling training to determine a second sampling phase adjustment to the first-initial sampling phase, the second sampling phase adjustment determined using phase information from at least one toggling edge of a first data burst and to adjust the data reception timing based on the phase information.
19. The method of claim 18, wherein: the first data burst includes a preamble having a preamble interval; and wherein the phase information is associated with at least one toggling edge of the preamble.
20. The method of claim 19, further comprising:
receiving the first data burst from a first data path and a second data burst from a second data path; wherein during the preamble interval,
receiving a first single-ended preamble signal of the first data burst from the first data path and a second single-ended preamble signal of a second data burst from the second data path; and
combining the first single-ended preamble signal and the second single-ended preamble signal to form a pseudo-differential signal during the preamble interval.
21. The method of claim 20, further comprising: retrieving a stored value from mode register storage representing a duration and a pattern of the preamble interval.
Prosecution Insights