Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated December 23, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed December 23, 2024 and November 12, 2025 have
been considered.
Claim Objections
Claims 2-5, 10, 11, 13-17, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 6-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2 and 5-7 of U.S. Patent No. 11830827 [‘827]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘827
1. A memory device, comprising: a memory cell comprising: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction; a dielectric fin structure extending along the first lateral direction, wherein the dielectric fin is disposed immediately next to the plurality of first nanostructures and next to the plurality of second nanostructures along a second lateral direction perpendicular to the first lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure, and wherein a second sidewall of each of the plurality of second nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall; and a second gate structure wrapping around each of the plurality of second nanostructures except for the second sidewall.
1. A memory device, comprising: a memory cell that randomly presents either a first logic state or a second logic state, the memory cell comprising: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures along the first lateral direction; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures along the first lateral direction; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure, the second lateral direction being perpendicular to the first lateral direction; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.
6. The memory device of claim 1, wherein the first gate structure includes a first gate dielectric layer configured to be broken down to present a first logic state for the memory cell, and the second gate structure includes a second gate dielectric layer configured to be broken down to present a second logic state for the memory cell.
2. The memory device of claim 1, wherein the memory cell further comprises: a plurality of fourth nanostructures extending along the first lateral direction; a plurality of fifth nanostructures extending along the first lateral direction and disposed at a first side of the plurality of fourth nanostructures along the first lateral direction; a plurality of sixth nanostructures extending along the first lateral direction and disposed at a second side of the plurality of fourth nanostructures along the first lateral direction, wherein a second sidewall of each of the plurality of fourth nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a second gate structure wrapping around each of the plurality of fourth nanostructures except for the second sidewall.
5. The memory device of claim 2, wherein the first gate structure includes a first gate dielectric layer configured to be broken down to present the first logic state for the memory cell, and the second gate structure includes a second gate dielectric layer configured to be broken down to present the second logic state for the memory cell.
7. The memory device of claim 6, wherein the memory cell is configured to randomly present either the first logic state or the second logic state.
“…a memory cell that randomly presents either a first logic state or a second logic state…” – see claim 1.
8. The memory device of claim 6, wherein the first and second gate structures are concurrently applied with a programming voltage to randomly break down one of the first gate dielectric layer or the second gate dielectric layer.
6. The memory device of claim 5, wherein the first and second gate structures are concurrently applied with a programming voltage to randomly break down one of the first gate dielectric layer or the second gate dielectric layer.
9. The memory device of claim 3, wherein the plurality of first nanostructures form a channel of a first programming transistor of the memory cell, and the plurality of second nanostructures form a channel of a second programming transistor of the memory cell.
7. The memory device of claim 2, wherein the plurality of first nanostructures form a channel of a first programming transistor of the memory cell, the plurality of second nanostructures form a channel of a second programming transistor of the memory cell, the plurality of third nanostructures form a channel of a first reading transistor of the memory cell, the plurality of fourth nanostructures form a channel of a second programming transistor of the memory cell, the plurality of fifth nanostructures form a channel of a third programming transistor of the memory cell, and the plurality of sixth nanostructures form a channel of a fourth reading transistor of the memory cell.
As can be seen from the above table, both, claim 1 of the application and claim 1 of the patent describe a very similar semiconductor architecture. They both require:
A memory cell with a "plurality of first nanostructures" extending along a first lateral direction.
A "dielectric fin structure" disposed immediately next to the first nanostructures along a second lateral direction (perpendicular to the first).
A "first gate structure" that wraps around each of the first nanostructures, leaving a specific side exposed (except for one sidewall).
However, the primary differences lie in the application’s addition of second nanostructures, a second gate structure, and the second nanostructures’ contact with the dielectric fin. The patent broadly discloses a structure utilizing a plurality of first nanostructures next to a dielectric fin, along with a first gate structure. The Application merely limits or defines how additional elements (second nanostructures and a second gate) interact with this established architecture.
Because the Application's claims only add predictable or duplicating features to the patent’s existing combination, the differences are patentably indistinct. Therefore, the Application's claims are an obvious variant of the patent.
For similar reasons, claims 6-9 are rejected over claims 1, 2 and 5-7 of patent ‘827.
Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11830827 [‘827]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘827
12. A memory device, comprising: a memory cell comprising: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction; a dielectric fin structure extending along the first lateral direction, wherein the dielectric fin is disposed immediately next to the plurality of first nanostructures and next to the plurality of second nanostructures along a second lateral direction perpendicular to the first lateral direction; a first gate structure wrapping around each of the plurality of first nanostructures except for a first sidewall of each of the plurality of first nanostructures that contacts the dielectric fin; and a second gate structure wrapping around each of the plurality of second nanostructures except for a second sidewall of each of the plurality of second nanostructures that contacts the dielectric fin.
1. A memory device, comprising: a memory cell that randomly presents either a first logic state or a second logic state, the memory cell comprising: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures along the first lateral direction; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures along the first lateral direction; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure, the second lateral direction being perpendicular to the first lateral direction; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.
As can be seen from the above table, both, claim 12 of the application and claim 1 of the patent share the fundamental architecture of a memory device with:
A plurality of nanostructures extending in a first lateral direction.
A dielectric fin structure extending immediately next to the nanostructures along a second lateral direction.
A gate structure wrapping around the nanostructures.
The patent defines a cell with “plurality of first nanostructures," "plurality of second nanostructures" (at a first side), and "plurality of third nanostructures" (at a second side). Because the Application defines both the first and second nanostructures being located adjacent to the dielectric fin in the second lateral direction, the structure described in the Application merely defines a subset of the components inherently or explicitly present in the patent. Additionally, because the memory cell layout, the use of a perpendicular dielectric fin, and the gate all around wrapping structures are substantially identical in material function and design layout, the patent contains sufficient overlapping architecture to support the claimed recitations of the Application.
Claims 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11830827 [‘827]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘827
18. A memory device, comprising: a memory cell comprising: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction; a dielectric fin structure extending along the first lateral direction, wherein the dielectric fin is disposed immediately next to the plurality of first nanostructures and next to the plurality of second nanostructures along a second lateral direction perpendicular to the first lateral direction; a first gate structure wrapping around each of the plurality of first nanostructures except for a first sidewall of each of the plurality of first nanostructures that contacts the dielectric fin, wherein the first gate structure includes a first gate dielectric layer configured to be broken down to present a first logic state for the memory cell; and a second gate structure wrapping around each of the plurality of second nanostructures except for a second sidewall of each of the plurality of second nanostructures that contacts the dielectric fin, wherein the second gate structure includes a second gate dielectric layer configured to be broken down to present a second logic state for the memory cell; wherein the memory cell is configured to randomly present either the first logic state or the second logic state.
1. A memory device, comprising: a memory cell that randomly presents either a first logic state or a second logic state, the memory cell comprising: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures along the first lateral direction; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures along the first lateral direction; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure, the second lateral direction being perpendicular to the first lateral direction; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.
As can be seen from the above table, both, claim 18 of the application and claim 1 of the patent share the fundamental architecture of a memory device with:
A plurality of nanostructures extending in a first lateral direction.
A dielectric fin structure extending immediately next to the nanostructures along a second lateral direction.
A gate structure wrapping around the nanostructures.
The patent defines a cell with “plurality of first nanostructures," "plurality of second nanostructures" (at a first side), and "plurality of third nanostructures" (at a second side). Because the Application defines both the first and second nanostructures being located adjacent to the dielectric fin in the second lateral direction, the structure described in the Application merely defines a subset of the components inherently or explicitly present in the patent. Additionally, because the memory cell layout, the use of a perpendicular dielectric fin, and the gate all around wrapping structures are substantially identical in material function and design layout, the patent contains sufficient overlapping architecture to support the claimed recitations of the Application.
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 2: The memory device of claim 1, wherein the memory cell further comprises: a plurality of third nanostructures extending along the first lateral direction and disposed on a first side of the plurality of first nanostructures along the first lateral direction; a third gate structure wrapping around each of the plurality of third nanostructures except for a third sidewall of each of the plurality of third nanostructures that contacts the dielectric fin; a plurality of fourth nanostructures extending along the first lateral direction and disposed on a second side of the plurality of first nanostructures along the first lateral direction; and a fourth gate structure wrapping around each of the plurality of fourth nanostructures except for a fourth sidewall of each of the plurality of fourth nanostructures that contacts the dielectric fin.
-with respect to claim 10: The memory device of claim 9, wherein the plurality of third nanostructures form a channel of a first reading transistor of the memory cell, the plurality of fourth nanostructures form a channel of a second reading transistor of the memory cell, the plurality of fifth nanostructures form a channel of a fifth reading transistor of the memory cell, and the plurality of sixth nanostructures form a channel of a sixth reading transistor of the memory cell.
-with respect to claim 13: The memory device of claim 12, wherein the memory cell further comprises: a plurality of third nanostructures extending along the first lateral direction and disposed on a first side of the plurality of first nanostructures along the first lateral direction; a third gate structure wrapping around each of the plurality of third nanostructures except for a third sidewall of each of the plurality of third nanostructures that contacts the dielectric fin; a plurality of fourth nanostructures extending along the first lateral direction and disposed on a second side of the plurality of first nanostructures along the first lateral direction; and a fourth gate structure wrapping around each of the plurality of fourth nanostructures except for a fourth sidewall of each of the plurality of fourth nanostructures that contacts the dielectric fin.
-with respect to claim 16: The memory device of claim 12, wherein the memory cell further comprises: a plurality of third nanostructures extending along the first lateral direction and disposed on a first side of the plurality of first nanostructures along the first lateral direction; a third gate structure wrapping around each of the plurality of third nanostructures except for a third sidewall of each of the plurality of third nanostructures that contacts the dielectric fin; a plurality of fourth nanostructures extending along the first lateral direction and disposed on the first side of the plurality of second nanostructures along the first lateral direction; and a fourth gate structure wrapping around each of the plurality of fourth nanostructures except for a fourth sidewall of each of the plurality of fourth nanostructures that contacts the dielectric fin.
-with respect to claim 19: The memory device of claim 18, wherein the memory cell further comprises: a plurality of third nanostructures extending along the first lateral direction and disposed on a first side of the plurality of first nanostructures along the first lateral direction; a third gate structure wrapping around each of the plurality of third nanostructures except for a third sidewall of each of the plurality of third nanostructures that contacts the dielectric fin; a plurality of fourth nanostructures extending along the first lateral direction and disposed on a second side of the plurality of first nanostructures along the first lateral direction; a fourth gate structure wrapping around each of the plurality of fourth nanostructures except for a fourth sidewall of each of the plurality of fourth nanostructures that contacts the dielectric fin. a plurality of fifth nanostructures extending along the first lateral direction and disposed on a first side of the plurality of second nanostructures along the first lateral direction; a fifth gate structure wrapping around each of the plurality of fifth nanostructures except for a fifth sidewall of each of the plurality of fifth nanostructures that contacts the dielectric fin; a plurality of sixth nanostructures extending along the first lateral direction and disposed on a second side of the plurality of second nanostructures along the first lateral direction; and a sixth gate structure wrapping around each of the plurality of sixth nanostructures except for a sixth sidewall of each of the plurality of sixth nanostructures that contacts the dielectric fin.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 July 29, 2026
Prosecution Insights