DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-21 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 12/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 12/23/2024. These drawings are review and accepted by the examiner.
Specification
This application does not contain an abstract of the disclosure as required by 37 CFR 1.72(b). An abstract on a separate sheet is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-16, 21 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Kulkarni et al (US 10,269,419 B2 hereinafter “Kulkarni”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Kulkarni, for example in Figs. 1-10, discloses an electrical device (e.g., device 320; in Fig. 3B related in Figs. 1-3A, 3C-3I, 4-10), comprising:
a memory circuit (e.g., memory 100; in Figs. 1-5 related in Figs. 6-10) including bit-cell circuits (see for example in Figs. 1-5 related in Figs. 6-10), each bit-cell circuit (e.g., 101 and 102; in Figs. 1-5 related in Figs. 6-10) including a memory cell (e.g., SRAM cell 101; in Figs. 1-5 related in Figs 6-10) and a read port (e.g., RD Port 102; in Figs. 1-5 related in Figs. 6-10), wherein:
the memory cell is electrically connected to a read word line at a read output voltage (e.g., RWL0; in Figs. 1-5 related in Figs. 6-10) and is electrically connected to the read port by the read word line (see for example in Figs. 1-5 related in Figs. 6-10), and
the read port is further connected to a read bit-line complement signal (e.g., Local RBL “LBL”; in Figs. 1-5 related in Figs. 6-10) at a write output logic voltage or at a read bit-line complement output voltage that is less than or equal to the write output logic voltage (see for example in Figs. 1-5 related in Figs. 6-10); and
a general input output circuit (see for example in Fig. 3B related in Figs. 1-3A, 3C-3I, 4-10) including a bit-line pre-charge control circuit (e.g., pre-charge 103; in Figs. 1-5 related in Figs. 6-10) and a voltage level shifter circuit (e.g., circuit MNr2; in Figs. 1-5 related in Figs. 6-10), wherein the read bit-line complement signal is connected to the bit-line pre-charge control circuit and to the voltage level shifter circuit (see for example in Figs. 1-5 related in Figs. 6-10).
The structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 2, Kulkarni, for example in Figs. 1-10, discloses wherein the read port includes an in-series stack of first and second NMOS transistors (within 102; in Figs. 1-5 related in Figs. 6-10). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, Kulkarni, for example in Figs. 1-10, discloses wherein the memory cell includes a bit node signal (e.g., n0; in Figs. 1-5 related in Figs. 6-10) at the write output logic voltage (e.g., Local RBL “LBL”; in Figs. 1-5 related in Figs. 6-10) and the bit node signal is connected to a gate of the first NMOS transistor (e.g., MNr1; in Figs. 1-5 related in Figs. 6-10). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, Kulkarni, for example in Figs. 1-10, discloses wherein the read word line at the read output voltage is connected to a gate of the second NMOS transistor (e.g., circuit MNr2; in Figs. 1-5 related in Figs. 6-10) and the read bit-line complement signal at the write output logic voltage or at the read bit-line complement output voltage is connected to a drain of the second NMOS transistor (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, Kulkarni, for example in Figs. 1-10, discloses wherein a voltage difference between a drain of the first NMOS transistor and a source of the second NMOS transistor is less than ± 0.15 V (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, Kulkarni, for example in Figs. 1-10, discloses wherein the general input output circuit includes an array of the general input output circuits, the bit-cell circuits are connected in rows and each of the rows of bit-cells are connected to different ones of the general input output circuits in the array of general input output circuits (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 8, Kulkarni, for example in Figs. 1-10, discloses wherein each of the general input output circuits in the array of general input output circuits include separate ones of the bit-line pre-charge control circuit and the voltage level shifter circuits connected to separate ones of latch circuits connected thereto (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 9, Kulkarni, for example in Figs. 1-10, discloses wherein the voltage level shifter circuits and the latch circuits carry the read output voltage (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 10, Kulkarni, for example in Figs. 1-10, discloses wherein the bit-line pre-charge control circuits carries the write output logic voltage or read bit-line complement voltage (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 11, Kulkarni, for example in Figs. 1-10, discloses wherein the bit-line pre-charge control circuit includes a pre-charge circuit, a keeper circuit and an inverter circuit, wherein the pre-charge circuit, the keeper circuit and the inverter circuit are connected to the read bit-line complement signal at a common node point (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, Kulkarni, for example in Figs. 1-10, discloses wherein the pre-charge circuit includes a PMOS transistor having a drain connected to the common node point (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above), a source is at the write output logic voltage or the read bit-line complement output voltage, and a gate connected to receive a read pre-charge complement signal at the write output logic voltage or at the read bit-line complement output voltage (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 13, Kulkarni, for example in Figs. 1-10, discloses wherein: the keeper circuit includes a first PMOS transistor having a drain connected to the common node point (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above), and a gate connected to receive a read keeper complement signal at the write output logic voltage or at the read bit-line complement output voltage, and a source of the first PMOS transistor connected to a drain of a second PMOS transistor of the keeper circuit (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above), a source of the second PMOS transistor is at the write output logic voltage or the read bit-line complement output voltage, a gate of the second PMOS transistor connected at a second common node point to connect a read bit-line signal, at the write output logic voltage or at the read bit-line complement output voltage, to the voltage level shifter circuit (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 14, Kulkarni, for example in Figs. 1-10, discloses wherein the bit-line pre-charge control circuit includes a power switch circuit connected to the pre-charge circuit at a common node point at the read bit-line complement output voltage (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 15, Kulkarni, for example in Figs. 1-10, discloses wherein the power switch control circuit includes a first PMOS transistor and a second PMOS transistor that are parallel-connected to each other at the common node point by a source of the first PMOS transistor and a source of the second transistor (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 16, Kulkarni, for example in Figs. 1-10, discloses wherein a source of the first PMOS transistor is at the write output logic voltage, a source of the second PMOS transistor is at the read output voltage, a gate of the first PMOS transistor is connected to a voltage level shifted turbo signal at a maximum of the write output logic voltage or the read output voltage and a gate of the second PMOS transistor is connected to a complement voltage level shifted turbo signal at the maximum of the write output logic voltage or the read output voltage (see for example in Figs. 1-5 related in Figs. 6-10, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 21, Kulkarni, for example in Figs. 1-10, discloses wherein the electrical device with the memory circuit and the general input output circuit are part of a computer (see for example in Figs. 1-5, 10 related in Figs. 6-9, as discussed above). Also, the structure in of prior art (Kulkarni) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kulkarni et al (US 10,269,419 B2 hereinafter “Kulkarni”) in view of Raj et al (US 11,955,169 B2 hereinafter “Raj”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 5, Kulkarni, for example in Figs. 1-10, discloses the claimed invention as discussed above (see for example in Figs. 3-5 related in Figs. 1-2, 6-10). However, Kulkarni is silent with regard to wherein the read word line is part of a clock-to-read word line signal pathway at the read output voltage.
In the same field of endeavor, Raj, for example in Figs. 1-4, discloses wherein the read word line is part of a clock-to-read word line signal pathway at the read output voltage (e.g., elements 300; in Fig. 3 related in Figs. 1-2, 4).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Kulkarni such as aging aware dynamic keeper apparatus and associated method (see for example in Figs. 1-10 of Kulkarni) by incorporating the teaching of Raj such as high-speed multi-port memory supporting collision (see for example in Figs. 1-4 of Raj), for the purpose of controlling a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier (Raj, see abstract).
The structure in of prior art (Kulkarni and Raj) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 17, the above Kulkarni/Raj, combination discloses further including a control circuit connected to receive a main clock signal at the read output voltage and connected to receive a turbo signal at the read output voltage (see for example in Figs. 1-5 related in Figs. 6-10 of Kulkarni and also see in Fig. 3 related in Figs. 1-2, 4 of Raj, as discussed above). Also, the structure in of prior art (Kulkarni and Raj) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 18, the above Kulkarni/Raj, combination discloses wherein the control circuit includes a first voltage level shifter connected to receive a read pre-charge complement signal at the read output voltage and a read keeper complement signal at the read output voltage and transmit the read keeper complement signal and the read pre-charge complement signal at the write output logic voltage or the read bit-line complement output voltage to the bit-line pre-charge circuit of the general input output circuit (see for example in Figs. 1-5 related in Figs. 6-10 of Kulkarni and also see in Fig. 3 related in Figs. 1-2, 4 of Raj, as discussed above). Also, the structure in of prior art (Kulkarni and Raj) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 19, the above Kulkarni/Raj, combination discloses wherein the controller further includes a second voltage level shifter to receive the turbo signal at the read output voltage and transmit a voltage level shifted turbo signal and a complement voltage level shifted turbo signal at a maximum of the write output logic voltage or of the read output voltage (see for example in Figs. 1-5 related in Figs. 6-10 of Kulkarni and also see in Fig. 3 related in Figs. 1-2, 4 of Raj, as discussed above). Also, the structure in of prior art (Kulkarni and Raj) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 20, the above Kulkarni/Raj, combination discloses further including a row decoder circuit connected to carry signals at the read output voltage to and from the control circuit and carry signal to and from the memory circuit at the read output voltage (see for example in Figs. 1-5 related in Figs. 6-10 of Kulkarni and also see in Fig. 3 related in Figs. 1-2, 4 of Raj, as discussed above). Also, the structure in of prior art (Kulkarni and Raj) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 07/18/2026
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