DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No.12,217,819. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 are anticipated by claims 1-20 of the patent..
Regarding claim 1, claim 1 of the patent recites a method for performing an in-memory computation, comprising:
outputting an update command to change at least one of a plurality of weights for a computation to be performed on a memory array storing the plurality of weights, when one of the plurality of weights is to be changed, before a write operation to change the one weight (claim 1, lines 3-7);
in response to receiving the update command being outputted, performing the write operation on the memory array by a memory controller to update the changed weight (claim 1, lines 8-10); and
disabling the write operation on the memory array until receiving a next update command to change at least one of the plurality of weights (claim 1, lines 11-13).
Regarding claim 2, claim 2 of the patent recites the method of claim 1, further comprising:
disabling a read operation to a plurality of memory cells of the memory array storing the plurality of weights for computation.
Regarding claim 3, claim 3 of the patent recites the method of claim 1, wherein performing the write operation comprises:
pre-charging to a supply voltage a bit line and a complementary bit line associated with one of a plurality of memory cells of the memory array storing the changed weight;
setting the bit line to a first logic value based on the changed weight associated with the update command;
setting the complementary bit line to a second logic value complementary to the first logic value based on the changed weight; and
setting a word line associated with the one of the memory cells of the memory array to logical one.
Regarding claim 4, claim 4 of the patent recites the method of claim 1, wherein disabling the write operation comprises:
disabling pre-charging a bit line and a complementary bit line associated with one of a plurality of memory cells of the memory array with an unchanged weight; and
disabling setting the bit line and setting the complementary bit line.
Regarding claim 5, claim 5 of the patent recites the method of claim 1, wherein disabling the write operation comprises setting a word line associated with one of a plurality of memory cells of the memory array with an unchanged weight to logical zero.
Regarding claim 6, claim 6 of the patent recites the method of claim 1, wherein disabling the write operation comprises setting a word line associated with one of a plurality of memory cells of the memory array with an unchanged weight to a floating state.
Regarding claim 7, claim 7 of the patent recites the method of claim 1, further comprising:
in response to receiving the update command associated with a first segment in the memory array, performing the write operation on the first segment and separately disabling the write operation on a second segment separate from the first segment in the memory array.
Regarding claim 8, claim 8 of the patent recites a computing device, comprising:
a memory array comprising a plurality of memory cells to store a plurality of weights for computation (claim 8, lines 2-3); and
a memory controller configured to control the memory cells, wherein the memory controller is configured to:
in response to an update command outputted before a write operation when one of the plurality of weights is to be changed, perform a write operation to change the one weight (claim 8, lines 9-11); and
disable the write operation until a next update command is received (claim 8, lines 12-13).
Regarding claim 9, claim 9 of the patent recites the computing device of claim 8, wherein the memory controller is configured to disable a read operation on the memory cells storing the plurality of weights for computation.
Regarding claim 10, claim 10 of the patent recites the computing device of claim 8, wherein the memory controller is configured to perform the write operation by:
pre-charging a bit line and a complementary bit line of the memory array associated with one of the memory cells for storing the changed weight;
setting the bit line to a first logic value based on the changed weight associated with the update command;
setting the complementary bit line to a second logic value complementary to the first logic value based on the changed weight; and
setting a word line associated with the one of the memory cells to logical one.
Regarding claim 11, claim 11 of the patent recites the computing device of claim 8, wherein the memory controller is configured to disable the write operation by:
disabling pre-charging a bit line and a complementary bit line associated with one of the memory cells with an unchanged weight; and
disabling setting the bit line and setting the complementary bit line.
Regarding claim 12, claim 12 of the patent recites the computing device of claim 8, wherein the memory controller is configured to disable the write operation by setting a word line associated with one of the memory cells with an unchanged weight to logical zero.
Regarding claim 13, claim 13 of the patent recites the computing device of claim 8, wherein the memory controller is configured to disable the write operation by setting a word line associated with one of the memory cells with an unchanged weight to a floating state.
Regarding claim 14, claim 14 of the patent recites the computing device of claim 8, wherein the memory controller is configured to perform the write operation on a first segment in the memory array and separately disable the write operation on a second segment separate from the first segment in the memory array, in response to the update command associated with the first segment.
Regarding claim 15, claim 15 of the patent recites the computing device of claim 8, further comprising a command generating circuit configured to output the update command when the one weight is to be changed with a different weight.
Regarding claim 16, claim 16 of the patent recites the computing device of claim 15, wherein the command generating circuit is coupled to the memory controller.
Regarding claim 17, claim 17 of the patent recites the computing device of claim 15, wherein the memory controller comprises the command generating circuit.
Regarding claim 18, claim 18 of the patent recites a computing-in-memory device, comprising:
a command generating circuit configured to, before a write operation is performed on a memory array for storing a plurality of weights for in-memory computation, output an update command when one of the plurality of weights is to be replaced; and
a controller coupled to the command generating circuit and configured to disable the write operation until receiving a next update command.
Regarding claim 19, claim 19 of the patent recites the computing-in-memory device of claim 18, wherein the controller is further configured to, in response to the update command, perform the write operation to update the one weight in the memory array.
Regarding claim 20, claim 20 of the patent recites the computing-in-memory device of claim 18, wherein the controller is configured to disable the write operation by:
disabling pre-charging a bit line and a complementary bit line associated with one of a plurality of memory cells of the memory array with an unchanged weight; and
disabling setting the bit line and setting the complementary bit line.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 8, 9 and 14-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tran (US 20220067499 cited by Applicant in the IDS filed on 12/23/2024).
Regarding claims 1, 8 and 18, Tran discloses a method for performing an in-memory computation, comprising:
outputting an update command (a command must be outputted before performing a write operation) to change at least one of a plurality of weights for a computation to be performed on a memory array (paragraph [007]) storing the plurality of weights, when one of the plurality of weights is to be changed, before a write operation to change the one weight (paragraph [0069], lines 3-4);
in response to receiving the update command being outputted, performing the write operation on the memory array by a memory controller to update the changed weight (paragraph [00068] and [0110], lines 33-34); and
disabling the write operation (Fig. 17B shows the write operation of array 1705 the write operation of array 1705 is disabled when the sensing circuitry 172 is coupled to the array 1705 during a verify or read operation of the array 1705, see Fig. 17C and paragraph [0103], lines 10-18) on the memory array until receiving a next update command to change at least one of the plurality of weights (Fig. 19 shows a bank (an array) of the set 1901 is verified after the bank has been written, that means the write operation on that bank must be disabled).
The memory controller in claim 8 is considered control circuitry 1093 in Fig.19).
The command generating circuit and the control circuit in claim 18 is considered 1722 and 1723 in Fig. 19.
Regarding claims 2 and 9, Tran discloses disabling a read operation to a plurality of memory cells of the memory array storing the plurality of weights for computation (Fig. 17B, array 1705).
Regarding claim 14: Tran (Fig. 19) discloses the computing device of claim 8,
wherein the memory controller is configured to perform the write operation on a first segment in the memory array and separately disable the write operation on a second segment separate from the first segment in the memory array, in response to the update command associated with the first segment.
Regarding claim 15: Tran discloses the computing device of claim 8, further
comprising a command generating circuit (any circuit that generates the wrt command) configured to output the update command when one of the plurality of weights is to be replaced with a different weight.
Regarding claim 16: Tran (Figs. 18 and 19) discloses the computing device of
claim 15, wherein the command generating circuit is coupled to the memory controller.
Regarding claim 17: Tran (Figs 19 and 20) discloses the computing device of
claim 15, wherein the memory controller comprises the command generating circuit.
Regarding claim 19: Tran discloses the memory controller of claim 18, wherein
the control circuit is further configured to, in response to the update command (wrt),
perform the write operation to update the one of the plurality of weights in the memory
array.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5, 10-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tran in view of Qiao (CN 112558919 A cited by Applicant in the IDS filed on 12/23/2024).
The only difference between claims 3 and 10 and Tran is that performing the
write operation comprises: pre-charging to a supply voltage a bit line and a complementary bit line associated with one of the memory cells for storing the updated
weight; setting the bit line to a first logic value based on an updated weight associated
with the update command; setting the complementary bit line to a second logic value
complementary to the first logic value based on the updated weight; and setting a word
line associated with the one of the memory cells of the memory array to logical one.
However, Qiao discloses the use of an SRAM device to store the weight values
and perform the writing operation by precharging the bit line BL and the reverse bit
line BLB to VDD, setting the bit line to 0 and the reverse bit line BLB to 1 and the word
line to logic 1.
"Q= 1, QB= 0, transistor T2, transistor T1 is conducted, Q is written as 0,
QB is written as 1. firstly pre-charging the bit line BL and the reverse bit line BLB
are pre-charged to VDD, when the memory calculating bit unit is selected and
written, bit line BL is reduced to 0, word line WL= 1, the transistor T3 and the
transistor T4 are on state. Because the reverse bit line BLB= 1, QB= 0, the reverse
bit line BLB will be charged through the transistor T4 to the QB; when the QB is
increased, the transistor T1 will be in the off state; Q= 1 will be discharged to 0
through the transistor T3 to the bit line BL, and the writing of Q = 0 is completed."
It would have been obvious to one having ordinary skill in the art to use an SRAM
device the use of an SRAM device to perform the writing operation by precharging the
bit line BL and the reverse bit line BLB to VDD, setting the bit line to 0 and the reverse
bit line BLB to 1 and the word line to logic 1 to store weight data in a memory device.
Regarding claims 4, 11 and 20: The combination of Tran and Qiao discloses the
method of claim 1, the computing of claim 8 and the memory controller of claim 18, wherein disabling the write operation comprises:
disabling pre-charging a bit line and a complementary bit line associated with one
of the memory cells with an unchanged weight; and
disabling setting the bit line and setting the complementary bit line.
After finishing the write operation, there is no write operation performed on any
cells with an unchanged weight; therefore, there is no precharging the bit line and the
complementary bit line and there is no setting the bit line and the complementary bit
line.
Regarding claims 5 and 12: The combination of Tran and Qiao discloses the
method of claim 1 and the computing device of claim 8, wherein disabling the write
operation comprises setting a word line associated with one of the memory cells with an
unchanged weight to logical zero.
For the memory cells with unchanged weight, there is no update; therefore, the
word lines are inactive.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over
Tran in view of Nagata (US 2009/0317968 cited by Applicant in the IDS filed on 12/23/2024).
The only difference between claims 6 and 13 and Tran is that disabling the write
operation comprises setting a word line associated with one of the memory cells with
unchanged weight to a floating state. However, Nagata discloses that when the data is
not written to a memory element, the non-selected word line is made to be in a floating
state. It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to disable the write operation (when data is not
written (unchanged data) to a memory cell by floating the word line associated with the
memory cell.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chih et al. (US 2022/0236869) discloses an SRAM-based cell for in-memory computing and hybrid computations/storage memory architecture.
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/HUAN HOANG/Primary Examiner, Art Unit 2827
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