Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated December 24, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed December 24, 2024 have been considered.
Claim Objections
Claims 4-6 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-3 and 7-11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 6-10 of U.S. Patent No. 12217815 [‘815]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘815
1. A memory testing system, comprising: at least one memory device; a power supply configured to provide a first reference voltage to the at least one memory device according to a first signal; and a first processor configured to provide the first signal and a second signal; and a second processor configured to receive the second signal and test the at least one memory device under the plurality of voltage levels according the second signal to generate a plurality of first testing results corresponding to the plurality of voltage levels, wherein the first processor is further configured to execute a first testing program and control the power supply by the first signal to vary the first reference voltage from a first voltage level of the plurality of voltage levels to a second voltage level of the plurality of voltage levels to generate the plurality of first testing results corresponding to the first testing program.
1. A memory testing system, comprising: at least one memory device; a power supply configured to provide a first reference voltage to the at least one memory device according to a control signal; and a processor configured to: provide the control signal to control the power supply to vary the first reference voltage among a plurality of voltage levels; and test the at least one memory device under the plurality of voltage levels to generate a plurality of first testing results corresponding to the plurality of voltage levels, wherein the processor is further configured to execute a first testing program and control the power supply to vary the first reference voltage from a first voltage level of the plurality of voltage levels to a second voltage level of the plurality of voltage levels to generate the plurality of first testing results corresponding to the first testing program, and execute a second testing program different from the first testing program and control the power supply to vary the first reference voltage from the first voltage level to the second voltage level to generate a plurality of second testing results corresponding to the second testing program, wherein the first voltage level is one of a lowest one of the plurality of voltage levels and a highest one of the plurality of voltage levels, and the second voltage level is another one of the lowest one of the plurality of voltage levels and the highest one of the plurality of voltage levels.
2. The memory testing system of claim 1, wherein the first processor is further configured to control the power supply to step up or down the first reference voltage.
2. The memory testing system of claim 1, wherein the processor is further configured to control the power supply to step up or down the first reference voltage.
3. The memory testing system of claim 1, wherein a difference between two adjacent voltage levels of the plurality of voltage levels is equal to a difference between another two adjacent voltage levels of the plurality of voltage levels.
3. The memory testing system of claim 1, wherein a difference between two adjacent voltage levels of the plurality of voltage levels is equal to a difference between another two adjacent voltage levels of the plurality of voltage levels.
7. The memory testing system of claim 1, wherein the first reference voltage has a first voltage level of the plurality of voltage levels during a first period, has a second voltage level of the plurality of voltage levels during a second period, and has a third voltage level of the plurality of voltage levels during a third period, the first period, the second period and the third period are arranged in order, the second voltage level is between the first voltage level and the third voltage level, and three of the plurality of first testing results correspond to the first voltage level, the second voltage level, and the third voltage level, respectively.
6. The memory testing system of claim 1, wherein the first reference voltage has a first voltage level of the plurality of voltage levels during a first period, has a second voltage level of the plurality of voltage levels during a second period, and has a third voltage level of the plurality of voltage levels during a third period, the first period, the second period and the third period are arranged in order, the second voltage level is between the first voltage level and the third voltage level, and three of the plurality of first testing results correspond to the first voltage level, the second voltage level, and the third voltage level, respectively.
8. The memory testing system of claim 1, wherein the at least one memory device comprises a first memory device and a second memory device different from each other; the power supply is further configured to provide the first reference voltage to the first memory device and provide a second reference voltage to the second memory device; and the first processor is further configured to control the power supply to vary the second reference voltage among the plurality of voltage levels.
7. The memory testing system of claim 1, wherein the at least one memory device comprises a first memory device and a second memory device different from each other; the power supply is further configured to provide the first reference voltage to the first memory device and provide a second reference voltage to the second memory device; and the processor is further configured to control the power supply to vary the second reference voltage among the plurality of voltage levels.
9. The memory testing system of claim 8, wherein the first processor is further configured to: execute a testing program to test the first memory device; and execute the testing program to test the second memory device; and the second processor is further configured to: generate a first testing result of the plurality of first testing results, the first testing result corresponding to the first reference voltage, and generate a second testing result of the plurality of first testing results, the second testing result corresponding to the second reference voltage.
8. The memory testing system of claim 7, wherein the processor is further configured to: execute a testing program to test the first memory device to generate a first testing result of the plurality of first testing results, the first testing result corresponding to the first reference voltage, and execute the testing program to test the second memory device to generate a second testing result of the plurality of first testing results, the second testing result corresponding to the second reference voltage.
10. The memory testing system of claim 8, wherein the first reference voltage has a first voltage level of the plurality of voltage levels during a first period, has a second voltage level of the plurality of voltage levels during a second period, and has a third voltage level of the plurality of voltage levels during a third period and the second reference voltage has the first voltage level during the third period, has the second voltage level during the second period, and has the third voltage level during the first period.
9. The memory testing system of claim 7, wherein the first reference voltage has a first voltage level of the plurality of voltage levels during a first period, has a second voltage level of the plurality of voltage levels during a second period, and has a third voltage level of the plurality of voltage levels during a third period and the second reference voltage has the first voltage level during the third period, has the second voltage level during the second period, and has the third voltage level during the first period.
11. The memory testing system of claim 8, wherein the first reference voltage is substantially equal to the second reference voltage.
10. The memory testing system of claim 7, wherein the first reference voltage is substantially equal to the second reference voltage.
As can be seen from the above table, claim 1 of the application captures the exact same core function (testing memory devices by varying reference voltages) as the one-processor of claim 1 of the patent. The addition of the second processor does not add a new, distinct inventive concept. Additionally, the variation between controlling a power supply with one processor versus using two communicating processors (a controller and a tester) is considered an obvious design choice. Therefore, coverage has already been given to the earlier filed patent application.
For similar reasons, claims 2, 3 and 7-11 are rejected over claims 1-3 and 6-10 of patent ‘815.
Claims 12 and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-18 of U.S. Patent No. 12217815 [‘815]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘815
12. A memory testing method, comprising: providing a first signal to a power supply to generate a first reference voltage to a first memory device; applying a testing signal to a processor to test the first memory device; testing the first memory device during the plurality of time periods in response to the first voltage level according to the testing signal; adjusting the first reference voltage from a first voltage level to a second voltage level during a plurality of time periods according to the first signal; and testing the first memory device during the plurality of time periods in response to the second voltage level according to the testing signal.
11. A memory testing method, comprising: providing a first reference voltage to a first memory device; adjusting the first reference voltage from a first voltage level to a second voltage level during a plurality of time periods; and testing the first memory device during the plurality of time periods in response to each of the first voltage level and the second voltage level, providing a second reference voltage to a second memory device different from the first memory device; adjusting the second reference voltage from one of the first voltage level and the second voltage level to another one of the first voltage level and the second voltage level during the plurality of time periods; and applying a testing signal to test the second memory device during the plurality of time periods in response to the second reference voltage, wherein testing the first memory device comprises applying the testing signal to the first memory device.
14. The memory testing method of claim 12, wherein the first reference voltage and the second reference voltage are substantially the same.
12. The memory testing method of claim 11, wherein the first reference voltage and the second reference voltage are substantially the same.
15. The memory testing method of claim 12, wherein adjusting the first reference voltage comprises adjusting the first reference voltage to the first voltage level at a first period of the plurality of time periods and adjusting the first reference voltage to the second voltage level at a second period of the plurality of time periods; and adjusting the second reference voltage comprises adjusting the second reference voltage to the first voltage level at the second period and adjusting the second reference voltage to the second voltage level at the first period.
13. The memory testing method of claim 11, wherein adjusting the first reference voltage comprises adjusting the first reference voltage to the first voltage level at a first period of the plurality of time periods and adjusting the first reference voltage to the second voltage level at a second period of the plurality of time periods; and adjusting the second reference voltage comprises adjusting the second reference voltage to the first voltage level at the second period and adjusting the second reference voltage to the second voltage level at the first period.
16. The memory testing method of claim 12, further comprising: stepping up one of the first reference voltage and the second reference voltage; and stepping down another one of the first reference voltage and the second reference voltage.
14. The memory testing method of claim 11, further comprising: stepping up one of the first reference voltage and the second reference voltage; and stepping down another one of the first reference voltage and the second reference voltage.
17. The memory testing method of claim 12, further comprising: generating a plurality of first testing results in response to the testing signal during the plurality of time periods; and generating a plurality of second testing results in response to the testing signal during the plurality of time periods, wherein a number of the plurality of first testing results, a number of the plurality of second testing results and a number of the plurality of time periods are the same.
15. The memory testing method of claim 11, further comprising: generating a plurality of first testing results in response to the testing signal during the plurality of time periods; and generating a plurality of second testing results in response to the testing signal during the plurality of time periods, wherein a number of the plurality of first testing results, a number of the plurality of second testing results and a number of the plurality of time periods are the same.
18. The memory testing method of claim 12, wherein adjusting the first reference voltage comprises: adjusting the first reference voltage to a third voltage level to test the first memory device for the third voltage level, the third voltage level is between the first voltage level and the second voltage level.
16. The memory testing method of claim 11, wherein adjusting the first reference voltage comprises: adjusting the first reference voltage to a third voltage level to test the first memory device for the third voltage level, the third voltage level is between the first voltage level and the second voltage level.
19. The memory testing method of claim 18, wherein adjusting the first reference voltage further comprises: adjusting the first reference voltage among a plurality of voltage levels including the first voltage level, the second voltage level and the third voltage level to test the first memory device for each of the plurality of voltage levels, wherein a difference between two adjacent voltage levels of the plurality of voltage levels is equal to a difference between another two adjacent voltage levels of the plurality of voltage levels.
17. The memory testing method of claim 16, wherein adjusting the first reference voltage further comprises: adjusting the first reference voltage among a plurality of voltage levels including the first voltage level, the second voltage level and the third voltage level to test the first memory device for each of the plurality of voltage levels, wherein a difference between two adjacent voltage levels of the plurality of voltage levels is equal to a difference between another two adjacent voltage levels of the plurality of voltage levels.
20. The memory testing method of claim 12, further comprising: executing a first testing program and controlling the first reference voltage to vary from the first voltage level to the second voltage level to generate a plurality of first testing results of the first memory device corresponding to the first testing program; and executing a second testing program different from the first testing program and controlling the first reference voltage to vary from the first voltage level to the second voltage level to generate a plurality of second testing results of the first memory device corresponding to the second testing program.
18. The memory testing method of claim 11, further comprising: executing a first testing program and controlling the first reference voltage to vary from the first voltage level to the second voltage level to generate a plurality of first testing results of the first memory device corresponding to the first testing program; and executing a second testing program different from the first testing program and controlling the first reference voltage to vary from the first voltage level to the second voltage level to generate a plurality of second testing results of the first memory device corresponding to the second testing program.
As can be seen from the above table, both, claim 12 of the application and claim 11 of the patent claim the core inventive concept of a memory testing method that adjusts a reference voltage from a first voltage level to a second voltage level during a plurality of time periods, while applying a testing signal. The application is merely a restatement or a subset of the patent. The patent anticipates the application because testing "a" first memory device according to multiple reference voltage levels encompasses the application's method of providing a first signal to a power supply to achieve the same voltage levels. Even if the claims are interpreted as having minor differences (e.g., application specifying a "processor" for the testing signal and "power supply" for the reference voltage), the application is an obvious variation of the patent. It is well known in the art that testing signals and reference voltages are generated, applied, and controlled by standard processors and power supplies. Using a processor to control a testing signal and a power supply to generate a reference voltage represents standard, predictable design choices.
For similar reasons, claims 14-20 are rejected over claims 11-18 of patent ‘815.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leobandung [US Patent Application # 20190182054].
With respect to claim 12, Leobandung discloses a memory testing method [fig. 10], comprising: providing a first signal to a power supply to generate a first reference voltage to a first memory device [The text states, "the process sets the first supply voltage level of memory 370 via voltage regulator 350" (e.g., providing a 101 supply voltage configuration value). The signal to set this configuration value acts as the signal to the power supply (voltage regulator) to generate the reference voltage – see par. 0064-0067]; applying a testing signal to a processor to test the first memory device [The reference states that "the process performs a write/read 0 test on memory 370 and stores results" and "performs a write/read 1 test." This execution implies an applied testing signal or command pattern (e.g., 10101... or 0101... initiated by the processor to test the memory – see par. 0064-0067]; testing the first memory device during the plurality of time periods in response to the first voltage level according to the testing signal [The text explains that the system logs the "start of the test time" in the cell map, sets the "first supply voltage level," and tests the memory by indicating "for each memory cell, whether the memory cell passed... or failed" – see par. 0064-0067]; adjusting the first reference voltage from a first voltage level to a second voltage level during a plurality of time periods according to the first signal [The method, shown in the text and fig. 10, involves a loop (or iteration) where the "process sets the first supply voltage level" at step 1020, and adjusts this configuration based on results to "identify a midpoint supply voltage" – see pars. 0064-0067 and fig. 10]; and testing the first memory device during the plurality of time periods in response to the second voltage level according to the testing signal [The text references a sequence of tests utilizing different voltage levels derived from "configuration tests" to isolate passing/failing cells. Iteratively testing across these different voltage levels forms the core of the described memory evaluation. – see pars. 0064-0067].
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 4: The memory testing system of claim 1, wherein the first processor is further configured to execute a second testing program different from the first testing program by sending the second signal to the second processor and control the power supply to vary the first reference voltage from the first voltage level to the second voltage level to generate a plurality of second testing results corresponding to the second testing program, wherein the first voltage level is one of a lowest one of the plurality of voltage levels and a highest one of the plurality of voltage levels, and the second voltage level is another one of the lowest one of the plurality of voltage levels and the highest one of the plurality of voltage levels.
-with respect to claim 13: The memory testing method of claim 12, further comprising: providing a second reference voltage to a second memory device different from the first memory device; adjusting the second reference voltage from one of the first voltage level and the second voltage level to another one of the first voltage level and the second voltage level during the plurality of time periods; and applying the testing signal to test the second memory device during the plurality of time periods in response to the second reference voltage.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 July 30, 2026
Prosecution Insights