DETAILED ACTION
This action is responsive to the following communications: the Application filed on December 24, 2024, and the Information Disclosure Statement filed on December 24, 2024.
Claims 1-20 are pending. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on December 24, 2024. This IDS has been considered.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0002], line 5, “even odd output data” should be –even output data--
In paragraph [0005], line 2, “provides to the output control signal to the data aligners” should be --provides the output control signal to the data aligners--.
In paragraph [0018], line 1, “each of the data aligners may 130_1 to 130_8 provide” should be --each of the data aligners 130_1 to 130_8 may provide--.
In paragraph [0021], line 1, “FIG. 1 and FIG. 2,, the data aligner 230 could be used to as one” should be --FIG. 1 and FIG. 2, the data aligner 230 could be used as one--.
In paragraph [0025], line 2, “The flip-flops FF1, FF2, the inverter IVT1 and the multiplexer MUX1 is a second stage aligner of the data aligner 230” should be --The flip-flops FF1, FF2, the inverter IVT1 and the multiplexer MUX1 are a second stage aligner of the data aligner 230--.
In paragraph [0029], line 2, “DQSOUT. the inverter IVT2 inverts” should be --DQSOUT. The inverter IVT2 inverts--.
In paragraph [0029], line 5, “sample the data” should be –samples the data--.
In paragraph [0038], line 3, “Operation of the DQS circuit 210 have been clearly explained” should be --Operation of the DQS circuit 210 has been clearly explained--.
In paragraph [0038], line 4, “Operation of each of the data aligners 130_1 to 130_8 have been clearly explained” should be --Operation of each of the data aligners 130_1 to 130_8 has been clearly explained--.
In paragraph [0044], line 1, “the output control signal 322 includes” should be --the output control signal generator 322 includes--.
In paragraph [0044], line 7, “output terminal of the trigger circuit 3212” should be --output terminal of the trigger circuit 3221--.
In paragraph [0048], line 1, “detailly” should be --in detail-- or --more specially--.
In paragraph [0048], line 9, “the trigger DQS signal DQS_DIV are complementary to each other” should be --the trigger DQS signal DQS_DIV in the odd case are complementary to each other--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9, which depends from claim 7, recites “a second inverter, configured to invert the synchronous control clock to generate an inverted synchronous control clock”. However, claim 7 already recites “a second inverter, configured to invert the output DQS signal to generate an inverted output DQS signal”. It is unclear whether the second inverter of claim 9 refers to the same second inverter previously recited in claim 7 or to an additional inverter. The same inverter cannot clearly be understood as both inverting the output DQS signal and inverting the synchronous control clock.
Accordingly, claim 9 fails to particularly point out distinctly claim the invention; therefore, claim 9 is indefinite under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, 9-11, 13 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. (US 20180174636).
Regarding independent claim 1, Jeon et al. disclose a data alignment circuit [Fig. 7: 330] of a memory device, comprising:
a data strobe (DQS) circuit [Fig. 7: 332], configured to generate an output DQS signal [the data strobe buffer 332 buffers the received data strobe signal DQS and may output an internal data strobe signal IDQS, para. 80];
a synchronous control circuit [Fig. 7: 350], coupled to the DQS circuit [see Fig. 7, the division circuit 350 coupled to the data strobe buffer 332], and configured to generate a synchronous control clock according to at least one device clock of the memory device and the output DQS signal [see Fig. 7, the division circuit 350 receives the clock signal CLK and the internal data strobe signal IDQS, divide the clock signal CLK and outputs an alignment control signal ACS by sampling the divided clock signal based on the internal data strobe signal IDQS, para. 84-86], and generate an output control signal according to the synchronous control clock and the output DQS signal [see Fig. 7, the selection signal generator 360 receives the internal data strobe signal IDQS, a trigger signal TRG, and the alignment control signal ACS and determines a logic level of the alignment control signal ACS at an edge of the internal data strobe signal IDQS. The selection signal generator 360 outputs a selection signal SS having a logic level which is based on a logic level of the alignment control signal ACS at the edge of the internal data strobe signal IDQS, para. 87]; and
a plurality of data aligners [see Fig. 7 with respect to Fig. 10, the data alignment block 400 includes a first alignment circuit 410 and a second alignment circuit 450, para 98], coupled to the DQS circuit and the synchronous control circuit [see Fig. 7 with respect to Fig. 10, the data alignment block 400 receives the first and second data sequences DSR and DSF from the data sampling circuit 340, the alignment control signal ACS and the selection signal SS, para. 91], wherein each of the plurality of data aligners samples a data according to the output DQS signal respectively [see Fig. 7, the data sampling circuit 340 receives the data sequence DS from the data buffer 331, and receives the internal data strobe signal IDQS from the data strobe buffer 332 and sample the data sequence DS based on IDQS. It samples at each of the rising and falling edges of IDQS to generate first and second data sequences DSR and DSF, para. 82] and outputs an output data according to the synchronous control clock and the output control signal respectively [see Fig. 7, the data alignment block 400 receives the first and second data sequences DSR and DSF from the data sampling circuit 340, the alignment control signal ACS and the selection signal SS and output the internal data DTA, para. 91].
Regarding claim 3, Jeon et al. disclose wherein one of the plurality of data aligners comprises:
a first sampling circuit [Fig. 7: 340], coupled to the DQS circuit, and configured to receive the data and the output DQS signal, and sample the data to a first node according to the output DQS signal [see Fig. 7 with respect to Fig. 8, the data sampling circuit 340 receives the data sequence DS from the data buffer 331, and receives the internal data strobe signal IDQS from the data strobe buffer 332 and sample the data sequence DS using IDQS, para. 82. The third sampler 343 samples the data sequence DSRX output from the first sampler 341 at a falling edge of the internal data strobe signal IDQS, para. 94].
Regarding claim 4, Jeon et al. disclose wherein one of the plurality of data aligners further comprises:
a first flip-flop [Fig. 11: 421, coupled to the first node, and configured to sample the data on the first node to be a first sampled data according to the synchronous control clock [see Fig. 11, the first alignment circuit 410 includes a first alignment block 420 that is controlled by the alignment control signal ACS. The first alignment block 420 includes a rising edge-triggered flip-flop 421, para. 101-102. The rising edge-triggered flip-flop 421 samples the first bit D1 in response to a rising edge of the alignment control signal ACS, para. 114];
a first inverter, configured to invert the synchronous control clock to generate an inverted synchronous control clock [Jeon et al. use rising edge-triggered flip-flop 421 and a falling edge-triggered flip-flop 431, both controlled by the alignment control signal ACS, para. 102-104. Functionally, a falling edge-triggered path is similar to using an inverted clock path];
a second flip-flop [Fig. 11: 431], coupled to the first node, and configured to sample the data on the first node to be a second sampled data according to the inverted synchronous control clock [see Fig. 11, the first alignment circuit 410 includes a second alignment block 430 that is controlled by the alignment control signal ACS. The second alignment block 430 includes a falling edge-triggered flip-flop 431, para. 101-104. The second alignment block 430 receives a second bit D3 of the first data sequence DSR in response to a falling edge of ACS, para. 115]; and
a multiplexer [Fig. 11: 441-444], coupled to the first flip-flop and the second flip-flop [see Fig. 11], and configured to output one of the first sampled data and the second sampled data to be the output data according to the output control signal [see Fig. 11, each of the plurality multiplexers 441, 442, 443 and 444 selects one of corresponding bits of the first parallel bits DRE1, DRE2, DRE3 and DRE4 and the second parallel bits DRO1, DRO2, DRO3 and DRO4 in response to the first selection signal SS1 and the second selection signal SS2 and outputs each selected bit as the first parallel data DPR1, DPR2, DPR3 and DPR4, para. 105].
Regarding claim 5, Jeon et al. disclose wherein the multiplexer selects the first sampled data to be the output data according to the output control signal having a first logic value, and selects the second sampled data to be the output data according to the output control signal having a second logic value [The first selection signal SS1 and the second selection signal SS2 are included in the selection signal SS and have different logic levels with respect to each other. Each of the plurality multiplexers 441-444 selects between first parallel bits and second parallel bits in response to SS1 and SS2, para. 105].
Regarding claim 6, Jeon et al. disclose wherein one of the plurality of data aligners further comprises:
a first latch circuit, coupled to the first flip-flop [Fig. 11: 422-424, the first alignment block 420 includes a rising edge-triggered flip-flop 421 and first latches 422, 423 and 424 which are connected in series, para. 102], and configured to latch the first sampled data [latches 422-424 latch the output of flip-flop 421, para. 114-116]; and
a second latch circuit, coupled to the second flip-flop [Fig. 11: 432-434, the second alignment block 430 includes a falling edge-triggered flip-flop 431 and second latches 432, 433 and 434 which are connected in series, para. 104], and configured to latch the second sampled data [latches 432-434 latch the output of flip-flop 431, para. 114-116].
Regarding claim 7, Jeon et al. disclose wherein one of the plurality of data aligners further comprises:
a second inverter, configured to invert the output DQS signal to generate an inverted output DQS signal [see Fig. 8, the first sampler 341 samples the internal data signal IDQ at a rising edge of the internal data strobe signal IDQS and the second sampler 342 samples the internal data signal IDQ at a falling edge of the internal data strobe signal IDQS, para. 93. Rising/falling edge sampling from IDQS is functionally equivalent to using complementary DQS phases]; and
a second sampling circuit [Fig. 8: 342], coupled to the DQS circuit, and configured to receive the data and the inverted output DQS signal, and sample the data to a second node according to the inverted output DQS signal [see Fig. 7 with respect to Fig. 8, the second sampler 342 receives the internal data signal IDQ and samples the internal data signal IDQ at a falling edge of the internal data strobe signal IDQS, para. 93].
Regarding claim 9, Jeon et al. disclose wherein one of the plurality of data aligners further comprises:
a third flip-flop [Fig. 12: 461, coupled to the second node, and configured to sample the data on the second node to be a third sampled data according to the synchronous control clock [see Fig. 12, the second alignment circuit 450 may include a first alignment block 460 that is controlled by the alignment control signal ACS. The first alignment block 460 includes a rising edge-triggered flip-flop 461, para. 107-108. The operation of the second alignment circuit 450 is substantially similar to the operation of the first alignment circuit 410 described with reference to FIG. 13, para. 119];
a second inverter, configured to invert the synchronous control clock to generate an inverted synchronous control clock [Jeon et al. use rising edge-triggered flip-flop 461 and a falling edge-triggered flip-flop 471, both controlled by the alignment control signal ACS, para. 108-110. Functionally, a falling edge-triggered path is similar to using an inverted clock path];
a fourth flip-flop [Fig. 12: 471], coupled to the second node, and configured to sample the data on the second node to be a fourth sampled data according to the inverted synchronous control clock [see Fig. 12, the second alignment circuit 450 includes a second alignment block 470 that is controlled by the alignment control signal ACS. The second alignment block 470 includes a falling edge-triggered flip-flop 471, para. 107-110. The operation of the second alignment circuit 450 is substantially similar to the operation of the first alignment circuit 410 described with reference to FIG. 13, para. 119].
Regarding claim 10, Jeon et al. disclose wherein at least one of the first flip-flop, the second flip-flop, the third flip-flop and the fourth flip-flop is implemented by a D type flip-flop [it would have been obvious for a person having ordinary skill in the art to implement at least one of Jeon et al.’s disclose edge triggered flip-flops as a D type flip flop because Jeon et al.’s flip-flops perform the conventional DFF function of sampling and holding an input data bit in response to a clock edge. A D type flip-flop is a well-known, predictable circuit element for edge triggered sampling and storage of data in synchronous memory alignment circuits. Therefore, selecting a D type implementation for at least one of Jeon et al.’s flip-flops would have been a routing design choice yielding the predictable result of capturing the input data value on the relevant clock edge].
Regarding claim 11, Jeon et al. disclose wherein one of the plurality of data aligners further comprises:
a third latch circuit, coupled to the third flip-flop [Fig. 12: 472-474, the first alignment block 460 includes a rising edge-triggered flip-flop 461 and first latches 462, 463 and 464 which are connected in series, para. 108], and configured to latch the third sampled data [see Fig. 12, latches 462-464 latch the output of flip-flop 461]; and
a fourth latch circuit, coupled to the fourth flip-flop [Fig. 12: 462-464, the second alignment block 470 includes a falling edge-triggered flip-flop 471 and first latches 472, 473 and 474 which are connected in series, para. 110], and configured to latch the fourth sampled data [see Fig. 12, latches 472-474 latch the output of flip-flop 471].
Regarding claim 13, Jeon et al. disclose wherein the synchronous control circuit [Fig. 7: 350] comprises:
a synchronous control clock generator [Fig. 7: 351], configured to generate the synchronous control clock according to the at least one device clock [see Fig. 7, the division circuit 350 receives the clock signal CLK and the internal data strobe signal IDQS, divide the clock signal CLK and outputs an alignment control signal ACS by sampling the divided clock signal based on the internal data strobe signal IDQS, para. 84-86. The frequence divider 351 outputs divided clock signal CLK_DV, para. 85]; and
an output control signal generator [Fig. 7: 360], coupled to the synchronous control clock generator, and configured to generate the output control signal according to the synchronous control clock and the output DQS signal [see Fig. 7, the selection signal generator 360 receives the internal data strobe signal IDQS, a trigger signal TRG, and the alignment control signal ACS and determines a logic level of the alignment control signal ACS at an edge of the internal data strobe signal IDQS. The selection signal generator 360 outputs a selection signal SS having a logic level which is based on a logic level of the alignment control signal ACS at the edge of the internal data strobe signal IDQS, para. 87].
Regarding claim 17, Jeon et al. disclose wherein the output control signal generator generates a trigger DQS signal according to the output DQS signal [see Fig. 17, the selection signal generator 360 uses IDQS to generate internal output signals TX and TY via first sampler 361 and delay element 362, para. 130-131], and decide a logic value of the output control signal according to the trigger DQS signal and the synchronous control clock [The selection signal generator 360 determines a logic level of the alignment control signal ACS at an edge of the internal data strobe signal IDQS and outputs a selection signal SS having a logic level based on that logic level, para. 87. See Fig. 17, the second sampler 363 samples the alignment control signal ACS based on the second output signal TY to output the first selection signal SS1. The inverter 364 inverts the first selection signal SS1 to output the second selection signal SS2, para. 131].
Regarding claim 18, Jeon et al. disclose wherein:
when a rising edge of the trigger DQS signal corresponds to a period of a first logic value of the synchronous control clock, the output control signal generator generates the output control signal having the first logic value, and when the rising edge of the trigger DQS signal corresponds to a period of a second logic value of the synchronous control clock, the output control signal generator generates the output control signal having the second logic value [The selection signal generator 360 determines a logic level of the alignment control signal ACS at an edge of the internal data strobe signal IDQS and outputs a selection signal SS having a logic level based on that logic level, para. 87. The alignment control signal ACS may have a different logic level at a rising edge of the internal data strobe signal IDQS, para. 88. The selection signal SS reflects whether ACS is high or low at the relevant DQS edge, para. 134].
Regarding claim 19, Jeon et al. disclose wherein the output control signal generator comprises:
a first trigger [Fig. 17: 361], coupled to the DQS circuit, and configured to generate the trigger DQS signal according to the output DQS signal [see Fig. 17, the first sampler 361 samples the trigger signal TRG based on the internal data strobe signal IDQS, to provide a first output signal TX, para. 131]; and
a second trigger [Fig. 17: 363], coupled to the first trigger, and configured to generate the output control signal according to the synchronous control clock and the trigger DQS signal [see Fig. 17, the second sampler 363 samples the alignment control signal ACS based on the second output signal TY to output the first selection signal SS1, para. 131].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 8, 12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20180174636) in view of Park et al. (US 9530472).
Regarding claim 2, Jeon et al. teach the limitations with respect to claim 1.
However, Jeon et al. are silent with respect to wherein the DQS circuit is implemented by one of a differential amplifier and a sensing amplifier.
Park et al. teach a data alignment circuit [see Fig. 1] of a memory device, comprising:
a data strobe (DQS) circuit [Fig. 1: 110], configured to generate an output DQS signal [see Fig. 1, the data strobe buffer 110 outputs the data strobe pulse signals DQSRP2 and DQSFP2, col. 2, lines 61-63], wherein the DQS circuit is implemented by one of a differential amplifier and a sensing amplifier [the data strobe buffer 110 buffers at least one data strobe signal DQS and DQSB, wherein the data strobe signal DQSB is an inversion signal of the data strobe signal DQS, col. 2, lines 61-64. The data strobe pulse signals DQSRP2 and DQSFP2 differentially amplified in the data strobe buffer 110, col. 3, lines 27-29].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park et al. to the teaching of Jeon et al. such that modifying Jeon et al.’s data alignment circuit by implementing its DQS buffer as the differential-type DQS buffer as taught by Park et al. to improve DQS signal integrity, reduce susceptibility to noise and maintain set-up/hold timing margin of data [see Park et al.’s col. 2, lines 25-31].
Regarding claim 8, Jeon et al. teach the limitations with respect to claim 7.
However, Jeon et al. are silent with respect to wherein each of the first sampling circuit and the second sampling circuit is implemented by one of a data latch circuit and a transmission gate.
Park et al. teach wherein each of the first sampling circuit and the second sampling circuit is implemented by one of a data latch circuit and a transmission gate [see Fig. 1, the latch 300 includes a latch 310 and a latch 320. Latch 310 latches data in synchronization with DQSRP2 and latch 320 latches data in synchronization with DQSFP2, col. 3, lines 17-25].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park et al. to the teaching of Jeon et al. such that implementing the first and second DQS sampling circuits of Jeon et al. as data latch circuits as taught by Park et al. to help ensure the set-up/hold timing margin of data [see Park et al.’s col. 2, lines 25-31].
Regarding claim 12, Jeon et al. teach the limitations with respect to claim 1.
However, Jeon et al. are silent with respect to wherein the DQS circuit generates the output DQS signal according to a DQS signal and a complementary DQS signal.
Park et al. teach a data alignment circuit [see Fig. 1] of a memory device, comprising:
a data strobe (DQS) circuit [Fig. 1: 110], configured to generate an output DQS signal [see Fig. 1, the data strobe buffer 110 outputs the data strobe pulse signals DQSRP2 and DQSFP2, col. 2, lines 61-63], wherein the DQS circuit generates the output DQS signal according to a DQS signal and a complementary DQS signal [the data strobe buffer 110 buffers at least one data strobe signal DQS and DQSB, wherein the data strobe signal DQSB is an inversion signal of the data strobe signal DQS, col. 2, lines 61-64. The data strobe pulse signals DQSRP2 and DQSFP2 differentially amplified in the data strobe buffer 110, col. 3, lines 27-29].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park et al. to the teaching of Jeon et al. such that modifying Jeon et al.’s data alignment circuit by implementing its DQS buffer as the differential-type DQS buffer as taught by Park et al. to improve DQS signal integrity, reduce susceptibility to noise and maintain set-up/hold timing margin of data [see Park et al.’s col. 2, lines 25-31].
Regarding claim 14, Jeon et al. teach the limitations with respect to claim 13.
However, Jeon et al. are silent with respect to wherein:
the at least one device clock comprises a first device clock and a second device clock, and the first device clock is complementary to the second device clock.
Park et al. teach a data alignment circuit [see Fig. 1] of a memory device, comprising the at least one device clock comprises a first device clock and a second device clock [Fig. 1: clocks CK and CKB], and the first device clock is complementary to the second device clock [the clock CKB is an inversion clock of the clock CK, col. 6, lines 29-31].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park et al. to the teaching of Jeon et al. such that modifying Jeon et al.’s data alignment circuit to use Park. et al.’s complementary clock pair CK/CKB to provide robust opposite phase clock timing for generating alignment timing signals, with the predictable result of a synchronous control circuit whose device clock input includes a first clock and a complementary second clock.
Regarding claim 15, Jeon et al. in combination with Park et al. teach the limitations with respect to claim 14.
Furthermore, Park et al. disclose wherein the synchronous control clock generator comprises:
a buffer [Fig. 3: 714], configured to provide a trigger clock according to the first device clock and the second device clock [the clock buffer 714 buffers the clocks CK and CKB and outputs a buffered clock to the clock driver 715, col. 6, lines 57-59]; and
a trigger circuit [Fig. 3: 715], coupled to the buffer [see Fig. 3], and configured to generate the synchronous control clock according to the trigger clock [the clock driver 715 drives the clock applied from the clock buffer 714 and outputs a driven clock to the flip-flop 713, col. 6, lines 59-61].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20180174636) in view of Park et al. (US 9530472) as applied to claim 15 above and further in view of Jain et al. (US 20110215842).
Regarding claim 16, Jeon et al. in combination with Park et al. teach the limitations with respect to claim 15.
Furthermore, Park et al. disclose wherein:
the buffer is implemented by one of a differential amplifier and a sensing amplifier [because CK and CKB are complementary, a person having ordinary skill in the art would have found it obvious to implement the clock buffer as a differential amplifier to receive the complementary clock pair and generate a robust trigger clock].
However, Jeon et al. in combination with Park et al. are silent with respect to the trigger circuit is implemented by a T type flip-flop.
Jain et al. disclose a programmable digital clock frequency signal divider module 100 has a secondary divider module 130 that includes a divide by two latch, in the form of a T-type flip flop 132 [para. 21]. Jain et al. further explains rising edges of the sequence of clock pulses trigger the divide by two latch (T-type flip flop 134) thereby resulting in a latch output clock signal OCS, with a 50% duty cycle at the output Q4 of the divide by two latch (T-type flip flop 134) [para. 26].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Jain et al. to the teaching of Jeon et al. in combination with Park et al. such that implementing the synchronous control clock of Park et al. with the known T-type flip-flop divider as taught by Jain et al. to predictably generate a stable divided clock suitable for high-speed DDR-type circuits.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20180174636) as applied to claim 19 above in view of Lee et al. (US 20180294026).
Regarding claim 20, Jeon et al. teach the limitations with respect to claim 19.
Furthermore, Jeon et al. disclose wherein the second trigger is implemented by a D type flip-flop [it would have been obvious for a person having ordinary skill in the art to implement the second sampler of Jeon et al. as a D type flip flop because the second sampler 363 samples the alignment control signal ACS based on the second output signal TY to output the first selection signal SS1 (para. 131). Therefore, selecting a D type implementation for Jeon et al.’s flip-flop 363 would have been a routing design choice].
However, Jeon et al. are silent with respect to the first trigger is implemented by a T type flip-flop.
Lee et al. teach in Figure 2 the divider circuit 300 dividing the second data strobe buffering signal DQS_b2 to generate a divided signal QF and a divided bar signal QFB [para. 37]. Lee et al. further disclose first flip-flop FF1 having a clock input terminal configured to receive the second data strobe buffering signal DQS_b2, an input receiving QFB and another input receiving QF from its own outputs [para. 38]. This feedback arrangement is a toggle structure, functionally corresponding to a T type flip-flop used to generate a divided DQS trigger signal.
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Lee et al. to the teaching of Jeon et al. such that implementing the output control signal generator of the data alignment circuit of Jeon et al. using Lee et al.’s DQS divider flip-flop to generate the output control signal with predictable timing alignment and reliability benefits.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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