DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 – 8 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are:
In claim 5, currently depend from claim 1, includes language “the third word line”, “the fourth word line”, “the source line”, “the bit line”, which lack antecedent bases and the essential elements for the claimed limitations, whereas claim 5 would appropriately be dependent from claim 3 where the bases for those elements are established.
Claims 6 – 8 are also rejected for being dependent from claim 5.
Similarly, claim 12 should be dependent from claim 11.
Appropriate correction is required in order to overcome this type of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 9, 10, 13, 14 and 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ueda et al. (US Pat Pub 2015/0187393).
Regarding claim 1, Ueda et al. disclose a bit cell (for example the top-left cell unit of fig. 1, and all related texts) comprising:
a variable resistor (top-left variable resistor of fig. 1) and a first transistor (top-left transistor in fig. 1 whose gate connects to line WLn) connected in series between a first end node (SL0) and a second end node (BL0, as shown in fig. 1), wherein a first gate of the first transistor is connected to a first word line (referred to as word line WLn, fig. 1); and
a second transistor (the second top-left transistor immediately below the first transistor in fig. 1) connected between the first end node (SL0) and the second end node (BL0, through a second variable resistor in series with the second transistor), wherein a second gate of the second transistor is connected to a second word line (referred to as word line WLn-1, fig. 1. Note that the claim does not clearly require that the second transistor be DIRECTLY CONNECTED between the first end node SL0 and the second end node BL0. Hence in this configuration, the second transistor is considered to be connected between said two end nodes).
Regarding claims 2 and 10, Ueda et al. also disclose he bit cell of claim 1, wherein the variable resistor is any of a resistive random-access memory-type variable resistor, a magnetic tunnel junction-type variable resistor, and a phase change memory-type variable resistor (see abstract: “resistive memory cell array”).
Regarding claim 13, Ueda et al. also disclose the in-memory computing circuit of wherein a resistance state of the variable resistor is switchable between at least a high resistance state and a low resistance state that is lower than the high resistance state, and wherein the high resistance state is indicative of a first bit value stored in the variable resistor and the second resistance state is indicative of a second bit value stored in the variable resistor (see para 0006, 0007, 0009, 0011, “high resistance” and “low resistance”).
Regarding claim 14, Ueda et al. also disclose the in-memory computing circuit of claim 13, wherein the low resistance state is indicative of a "1" bit value stored in the variable resistor and the high resistance state is indicative of a "0" bit value stored in the variable resistor (see para 0006 and 0053, “0” and “1” data).
Regarding claims 9 and 20, Ueda et al. also disclose a computing method comprising storing bit values in bit cells of array of bit cells arranged in rows and columns (as shown in frig. 1) wherein the bit cells each includes:
a variable resistor (top-left variable resistor of fig. 1) and a first transistor (top-left transistor in fig. 1 whose gate connects to line WLn) connected in series between a first end node (SL0) and a second end node (BL0, as shown in fig. 1), wherein a first gate of the first transistor is connected to a first word line (referred to as word line WLn, fig. 1); and
a second transistor (the second top-left transistor immediately below the first transistor in fig. 1) connected between the first end node (SL0) and the second end node (BL0, through a second variable resistor in series with the second transistor), wherein a second gate of the second transistor is connected to a second word line (referred to as word line WLn-1, fig. 1. Note that the claim does not clearly require that the second transistor be DIRECTLY CONNECTED between the first end node SL0 and the second end node BL0. Hence in this configuration, the second transistor is considered to be connected between said two end nodes), and
wherein the bit cells in the columns are connected in series forming bit cell stacks (as shown in fig. 1) and
performing a read operation to concurrently compute majority functions directed to stored bit values in selected rows of the bit cell stacks (see para 0010, 0012, 0018, and 0034 – 0039, etc…).
Allowable Subject Matter
Claim 3, 4, 11, 12 and 15 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the bit cell as set forth above, further comprising, in combination, the features and limitations additionally claimed at least in claims 3, 11, 12, and 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
See additional cited references for related disclosures to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 July 29, 2026
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