DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 7, it recites “adjusting a voltage value Eps of the lower portion of the lift pin and an average value Eesc of the voltage of the electrostatic attraction electrode during the processing of the wafer so as to match the predicted value Vdcs of the self-bias voltage of the wafer when an average value of a voltage of the electrostatic attraction electrode is set as Eesc”. Based on the limitation “adjusting a voltage value Eps of the lower portion of the lift pin and an average value Eesc of the voltage of the electrostatic attraction electrode during the processing of the wafer”, both the voltage value Eps and the average value Eesc are adjusted during the processing of the wafer. However, the limitation “to match the predicted value Vdcs of the self-bias voltage of the wafer when an average value of a voltage of the electrostatic attraction electrode is set as Eesc” indicates that the average value Eesc is set before the process in order to calculate the predicted value Vdcs.
Regarding claims 8-12, they are indefinite due to their dependency on claim 7.
Allowable Subject Matter
Claims 7-12 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office Action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the closest prior art of Bluck et al. (US20100208409) discloses a plasma processing method for processing a wafer located inside a plasma processing apparatus having a processing chamber disposed inside a vacuum container (abstract and Fig. 1), the processing chamber configured to generate plasma inside (paragraph 0072); a wafer stage disposed inside the processing chamber (paragraph 0074 and Fig. 1); an electrostatic chuck comprising a film-shaped electrostatic attraction electrode disposed in a dielectric film covering an upper surface of the wafer stage, the film-shaped electrostatic attraction electrode being configured to electrostatically attract the wafer placed on the dielectric film (paragraph 0074 and Fig. 1); a radio frequency electrode disposed inside the wafer stage, the radio frequency electrode being configured to be supplied radio frequency power during processing of the wafer (paragraph 0079 and Fig. 1); and a lift pin disposed inside the wafer stage, the lift pin being configured to move the wafer up and down by movement thereof in an up and down direction, and a lower portion of the lift pin being connected to a member made of a conductor (paragraphs 0077 and 0081). However, Bluck fails to disclose setting an electrical resistance value Rps between a direct current power source and the lower portion of the lift pin electrically connected to the direct current power source as recited in the instant calim, and adjusting a voltage value Eps of the lower portion of the lift pin during the processing of the wafer. None of the cited prior art of record, taken either alone or in combination, discloses or renders obvious a method comprising the missing limitations in the context of the instant claim.
Regarding claims 8-12, they are dependent on claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nagami et al. (US20140231389) discusses a plasma processing method wherein lift pins are configured to load/unload a semiconductor wafer on a wafer stage by moving up and down, wherein the lift pins are made of an insulating material such as a resin or ceramic and supported on a ring-shaped horizontal elevating plate connected to an elevation driving shaft of an actuator formed of an air cylinder or a ball screw device (paragraphs 0048 and 0053).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIONG-PING LU whose telephone number is (571) 270-1135. The examiner can normally be reached on M-F: 9:00am – 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua L Allen, can be reached at telephone number (571)270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JIONG-PING LU/
Primary Examiner, Art Unit 1713
