Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated December 31, 2024 claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed December 31, 2024 have been considered.
Claim Objections
Claims 2-7, 16-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 8, the claim states that the decoding circuit arrangement acts "responsive to the read enable signal," but the claim only recites that the control circuit receives the read enable signal. It does not explicitly state that the decoding circuit receives this signal or gets it from the control circuit.
In claim 8, the claim recites a single "latched address" as comprising a read address in the first half and a write address in the second half can appear confusing. An address is typically a single digital value at a given time, rather than "comprising" temporally split values.
Claims 9-14 are rejected because they depend on the indefiniteness of the claims from which they depend.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Masao [JP 2008118628 A].
With respect to claim 1, Masao discloses a memory circuit [3rd to the last paragraph of the Description] comprising: a control circuit configured to receive a clock signal comprising a clock cycle ["the memory is operated at twice the operating frequency... read with the first half clock, and accessed with the second half clock" - The claim introduces a standard clock cycle that the control circuit splits into timing phases, aligning with the Masao’s text mention of clock-based operations.] and output a plurality of control signals based on the clock signal ["switching between them makes it possible..." - The control circuit generates internal timing/control signals to coordinate when the memory switches between read and write modes during that single clock cycle.]; an input circuit arrangement configured to, responsive to the plurality of control signals, pass a latched address to an output of the input circuit arrangement, the latched address comprising, during a first half of the clock cycle, a read address received at a first input port and, during a second half of the clock cycle, a write address received at a second input port [“read with the first half clock, and accessed [written] with the second half clock. ... the address to be written on the decoder side is the address from which data was read before that" - This maps the first-half/second-half timing division directly to swapping the active addresses (read address first, write address second) at the memory inputs.]; an array of single-port memory cells, wherein the memory circuit is configured to perform a read operation during the first half of the clock cycle and a write operation during the second half of the clock cycle ["the interleave memory and deinterleave memory configured with a single port memory can be made into a pseudo two-port memory." - By executing one read and one write operation sequentially within the two halves of a single clock cycle, a single physical port behaves like two separate ports (pseudo two-port operation).]; and a decoding circuit arrangement configured to, based on the latched address at the output of the input circuit arrangement, activate a row of memory cells of the array during each of the first and second halves of the clock cycle ["the interleave memory and deinterleave memory configured with a single port memory can be made into a pseudo two-port memory." - By executing one read and one write operation sequentially within the two halves of a single clock cycle, a single physical port behaves like two separate ports (pseudo two-port operation).]. It is noted that the Masao reference indicates that the memory can access two different addresses (or rows) inside a single clock cycle—one for reading and one for writing.
Claim(s) 15 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Masao [JP 2008118628 A].
With respect to claim 15, Masao discloses a method of operating a memory circuit [3rd to the last paragraph of the Description], the method comprising: receiving, at a control circuit, a clock signal comprising a clock cycle ["the memory is operated at twice the operating frequency... read with the first half clock, and accessed with the second half clock" - The claim introduces a standard clock cycle that the control circuit splits into timing phases, aligning with the Masao’s text mention of clock-based operations.]; outputting a plurality of control signals from the control circuit based on the clock signal ["switching between them makes it possible..." - The control circuit generates internal timing/control signals to coordinate when the memory switches between read and write modes during that single clock cycle.]; in response to the plurality of control signals, passing a latched address to an output of an input circuit arrangement, wherein the latched address comprises, during a first half of the clock cycle, a read address received at a first input port and, during a second half of the clock cycle, a write address received at a second input port [“read with the first half clock, and accessed [written] with the second half clock. ... the address to be written on the decoder side is the address from which data was read before that" - This maps the first-half/second-half timing division directly to swapping the active addresses (read address first, write address second) at the memory inputs.]; performing a read operation on a first row of memory cells of an array of single- port memory cells during the first half of the clock cycle by using a decoding circuit arrangement to activate the first row of memory cells based on the latched address ["the interleave memory and deinterleave memory configured with a single port memory can be made into a pseudo two-port memory." - By executing one read and one write operation sequentially within the two halves of a single clock cycle, a single physical port behaves like two separate ports (pseudo two-port operation).]; and performing a write operation on a second row of memory cells of the array during the second half of the clock cycle by using the decoding circuit arrangement to activate the second row of memory cells based on the latched address ["the interleave memory and deinterleave memory configured with a single port memory can be made into a pseudo two-port memory." - By executing one read and one write operation sequentially within the two halves of a single clock cycle, a single physical port behaves like two separate ports (pseudo two-port operation).]. It is noted that the Masao reference indicates that the memory can access two different addresses (or rows) inside a single clock cycle—one for reading and one for writing.
With respect to claim 19, Masao discloses the using the decoding circuit arrangement to activate the first and second rows of memory cells comprises using the decoding circuit arrangement to activate a same row of memory cells. Masao shows that by operating at twice the frequency, the first half-clock performs one operation and the second half-clock accesses the identical physical row for the complementary operation, enabling a single-port memory to function as a pseudo two-port memory [3rd to the last paragraph of the Description].
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 2. The memory circuit of claim 1, wherein the input circuit arrangement comprises: a first latch circuit configured to latch the write address responsive to a first control signal of the plurality of control signals having a first logical state; and a second latch circuit configured to latch the read address responsive to a second control signal of the plurality of control signals having the first logical state.
-with respect to claim 6. The memory circuit of claim 1, wherein the row of memory cells is one row of a plurality of rows of memory cells of the array, and the plurality of rows of memory cells comprises a number of rows of memory cells exponentially related to a number of logical states of the latched address.
-with respect to claim 7. The memory circuit of claim 1, wherein each single-port memory cell of the array of single-port memory cells comprises a static random access memory (SRAM) cell.
-with respect to claim 16. The method of claim 15, wherein the passing the latched address to the output of the input circuit arrangement comprises: in response to a first control signal of the plurality of control signals, latching the write address with a first latch circuit during each of the first and second halves of the clock cycle; and in response to a second control signal of the plurality of control signals, latching the read address with a second latch circuit during the first half of the clock cycle.
-with respect to claim 18. The method of claim 15, wherein the receiving the clock signal at the control circuit comprises receiving a read enable signal and a write enable signal at the control circuit, the outputting the plurality of control signals from the control circuit is based on the read enable signal and the write enable signal, the using the decoding circuit arrangement to activate the first row of memory cells is based on the read enable signal, and the using the decoding circuit arrangement to activate the second row of memory cells is based on the write enable signal.
-with respect to claim 20. The method of claim 15, wherein the using the decoding circuit arrangement to activate the first and second rows of memory cells comprises using the decoding circuit arrangement to activate corresponding six-transistor static random access memory (SRAM) cells.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 September 3, 2026
Prosecution Insights