Prosecution Insights
Last updated: August 17, 2026
Application No. 19/007,022

CHARGE PUMP SYSTEM WITH LOW RIPPLE OUTPUT VOLTAGE

Non-Final OA §DP
Filed
Dec 31, 2024
Priority
Oct 18, 2019 — divisional of 11/336,174 +2 more
Examiner
LEBOEUF, JEROME LARRY
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
439 granted / 515 resolved
+17.2% vs TC avg
Moderate +7% lift
Without
With
+7.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
22 currently pending
Career history
541
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.4%
+6.4% vs TC avg
§102
26.3%
-13.7% vs TC avg
§112
21.9%
-18.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 515 resolved cases

Office Action

§DP
DETAILED ACTION As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 11, and 18 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 11, and 16 respectively, of U.S. Patent No. 11757356 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim recites substantially the same subject matter as the patented claims. Allowable Subject Matter Claim(s) 1-20 is/are objected to as being subject to a double patenting rejection, but would be allowable if a terminal disclaimer were filed. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not appear to disclose (as recited in claim 1): at least one of the plurality of input level detection circuit branches includes a first PMOS transistor and a first NMOS transistor and wherein a source terminal of the first NMOS transistor is configured to connect to a drain terminal of a current mirror NMOS transistor that is part of a current mirror configuration. The prior art does not appear to disclose (as recited in claim 11): at least one of the plurality of input level detection circuit branches includes a first PMOS transistor and a first NMOS transistor and wherein a source terminal of the first NMOS transistor is configured to connect to a drain terminal of a current mirror NMOS transistor that is part of a current mirror configuration. The prior art does not appear to disclose (as recited in claim 18): a source terminal of the first NMOS transistor is configured to connect to a drain terminal of a current mirror NMOS transistor that is part of a current mirror configuration; based on a value of the one or more enable signals, selecting a clock signal frequency from a plurality of predetermined frequencies; and modifying the output voltage of the charge pump device based on the selected clock signal frequency. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chou, US 20070063761 A1 does not appear to disclose a mirror configuration. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 07/23/2026
Read full office action

Prosecution Timeline

Dec 31, 2024
Application Filed
Jul 27, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

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Patent 12682950
SEMICONDUCTOR STORAGE DEVICE
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BIT LINE PRE-CHARGE VOLTAGE GENERATING CIRCUIT IN SEMICONDUCTOR MEMORY DEVICES FOR REDUCING CURRENT CONSUMPTION
1y 11m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
92%
With Interview (+7.2%)
2y 0m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 515 resolved cases by this examiner. Grant probability derived from career allowance rate.

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