DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishi et al. [EP 1 039 509 A1].
Regarding claims 1 and 16, Nishi et al. discloses an apparatus (Fig. 1) / a method (Fig. 12) for providing sensor data, comprising:
a multiplexer unit (Fig. 11, item 122A/B);
an analogue-to-digital converter unit (124A/B); and
a digital filter device (126),
wherein: the multiplexer unit (122A/B) is configured to: i) receive a number N of analogue sensor signals from N sensors (19, 86A/B, 96A/B) of an optical system (IL/PL) via N channels (SS1-SS4), N being at least one (as shown in Fig. 11, see also paragraph [0124] teaches the sensor signals); and ii) provide to the analogue-to-digital converter unit (124A/B) an analogue signal sequence comprising N multiplexed analogue sensor signals (as shown in Fig. 11, see also paragraph [0138] teaches the multiplexer unit and the ADC);
the analogue-to-digital converter (124A/B) is configured to convert the analogue signal sequence into a digital signal sequence comprising N digital sensor signals (paragraphs [0135]-[0139] teaches the process of obtaining the signals from the sensors to conversion of the signals);
the analogue-to-digital converter (124A/B) is configured to provide the N digital sensor signals (paragraph [0167] teaches the processor) to the digital filter device (126);
the digital filter device (126) is configured to filter the N digital sensor signals in a channel-specific manner to provide and store a respective filtered digital sensor signal for each of the N channels (paragraphs [0155]-[0158], [0168]-[0171] teaches the filtering of the signals); and
the analogue-to-digital converter (124A/B) and the digital filter device (126) have the same frequency-synchronized system clock (paragraphs [0135]-[0139], [0167] teaches the synchronized triggering system).
Regarding claim 2, Nishi et al. discloses further comprising: a control unit configured to clock-synchronously control the analogue-to-digital converter and the digital filter device via the frequency-synchronized system clock (paragraphs [0135]-[0139], [0167] teaches the synchronized triggering system).
Regarding claims 13-15, Nishi et al. discloses wherein the apparatus does not comprises an analogue filter, an optical system, comprising: an apparatus, wherein the apparatus is a lithography apparatus, a lithography apparatus, comprising: an optical system which comprises the apparatus (as shown in Fig. 1, see also paragraphs [0053]-[0072] teaches the apparatus and the optical systems).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nishi et al. in view of De Groot et al. [US 2007/0171425 A1].
Regarding claim 3, Nishi et al. discloses the apparatus, as applied above.
Nishi et al. does not teach comprising N digital filters.
However, De Groot et al. discloses a sensor system comprising a plurality of digital filters per channel (as show in Fig. 22B, see also paragraphs [0176]-[0177]).
Therefore, it would have been obvious to one of ordinary skill in the art to provide a plurality of digital filters per channel, as taught by De Groot et al. in the system of Nishi et al. because such a modification provides a suitable alternative configuration to provide the expected outcome of reducing response time of the apparatus.
Claims 4, 6-8, 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nishi et al. in view of Neefs et al. [WO 2017/089391 A1].
Regarding claims 4 and 6, Nishi et al. discloses the apparatus, as applied above.
Nishi et al. does not teach a storage unit, connected downstream of the N digital filters, with N memory locations or wherein the digital filter device comprises delay units for receiving the digital signal sequence.
However, Neefs et al. discloses means to enable accurate measurements of conditions prevailing within a lithographic apparatus comprising a sensor system comprising memory locations for storing the digital sensor signals (paragraphs [0069]-[0070], see also Fig. 5) and the use of a delay unit for receiving the signal into the memory (paragraph [0080], see also Fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art to provide N memory locations and delay units for receiving the digital signal, as taught by Neefs et al. in the system of Nishi et al. because such a modification provides a suitable alternative configuration to provide the expected outcome of reducing response time of the apparatus.
Regarding claims 7 and 8, Nishi et al. in view of Neefs et al. discloses further comprising an adding unit and a storage unit, wherein: a respective multiplier unit is connected downstream of each of the M delay units; each multiplier unit is assigned a specific filter coefficient; the delay units are configured to supply the memory contents of a specific channel of the N channels to the M multiplier units in accordance with the system clock; the M multiplier units are configured to multiply the memory contents supplied by the M delay units by the specific filter coefficients; the adding unit is connected downstream of the M multiplier units; the adding unit is configured to add up products of the multiplications provided by the M multiplier units to provide the filtered digital sensor signal of the specific channel; the storage unit is connected downstream of the adding unit; the storage unit comprises N memory locations; each of the N memory locations is assigned to exactly one of the N channels; and the respective memory location is configured for storing the respective filtered digital sensor signal for the respective one of the N channels, wherein the control unit is configured to clock-synchronously control the multiplexer unit, the analogue-to-digital converter, the delay units and the storage unit via the frequency-synchronized system clock (paragraphs [0135]-[0137], [0155]-[0157], see also Fig. 11 of Nishi et al. and Fig. 5 of Neefs et al.).
Regarding claims 10 and 11, Nishi et al. in view of Neefs et al. discloses comprising a processor device which comprises the digital filter device, the storage unit and the control unit, wherein the processor device further comprises a signal analysis unit configured to: i) analyse the digital sensor signals and/or the filtered digital sensor signals; and ii) adapt in dependence thereon at least one property of the digital filter device and/or a sampling frequency of the analogue-to-digital converter (paragraphs [0173], [0185], see also Figs. 14 and 15 of Nishi et al. and Fig. 5 of Neefs et al.).
Claims 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nishi et al. as modified in view of Sogard [US 2012/0099089 A1].
Regarding claims 5 and 9, Nishi et al. as modified discloses the apparatus, as applied above.
Nishi et al. as modified does not teach further comprising a digital-to-analogue converter connected between the control unit and the N sensors.
However, Sogard discloses a system for measuring dimensional changes and distortion wherein they system comprises a digital-to-analogue converter connected between the control unit and the N sensors (Fig. 12, see also paragraph [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art to provide a digital-to-analogue converter as taught by Sogard in the system of Nishi et al. as modified because such a modification provides a suitable alternative configuration to improve signal quality of the apparatus.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nishi et al. in view of Holz et al. [US 10,678,151 B2].
Regarding claim 12, Nishi et al. discloses the apparatus, as applied above.
Nishi et al. does not teach further comprising a vacuum housing which houses the N sensors and the multiplexer unit.
However, Holz et al. an assembly having a plurality of sensors and/or actuators controlled by a control device comprising a multiplexer wherein the multiplexer and the sensors are arranged in a vacuum housing (Col. 8 line 30-Col. 9 line 40, see also Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art to provide a vacuum housing, as taught by Holz et al. in the system of Nishi et al. because such a modification provides a suitable alternative configuration reduces the cables for the signal transmission (Col. 10 line 31-line 36 of Holz et al.).
Claims 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Nishi et al. in view of Garrity et al. [US 2023/0128469 A1].
Regarding claims 17-21, Nishi et al. discloses an apparatus a method (Fig. 12) / (Fig. 1), comprising:
an analogue-to-digital converter (Fig. 11, 124A/B) configured to convert analogue sensor signals into digital sensor signals (paragraphs [0135]-[0139] teaches the process of obtaining the signals from the sensors to conversion of the signals);
a digital filter device (126) connected downstream of the analogue-to-digital converter (Fig. 11, 124A/B), the digital filter device having low-pass behaviour to filtering the digital sensor signals which include a used signal component with used signal frequencies of a used signal bandwidth (paragraphs [0155]-[0158], [0168]-[0171] teaches the filtering of the signals).
Nishi et al. does not teach an interference signal component with at least one determinable alias frequency of a known interference frequency undersampled by the analogue-to-digital converter in the analogue sensor signal, and wherein the sampling frequency of the analogue-to-digital converter and the filter order of the digital filter device are configured so that the at least one alias frequency lies outside the used signal bandwidth and the sampling frequency is not a submultiple of the interference frequency and so that the digital filter device allows the signal components within the used signal bandwidth to pass and suppresses the at least one alias frequency of the undersampled interference signal components.
However, Garrity et al. disclose a device detecting the desired signals while reducing the noise using a notch filter wherein signal suppression at multiple defect or undesirable frequencies can occur (paragraphs [0092], [0096] and [0101]-[0105]).
Therefore, it would have been obvious to one of ordinary skill in the art to provide a filter to suppress at least one alias frequency of the interference signal components, as taught by Garrity et al. in the system of Nishi et al. because such a modification provides a suitable alternative configuration to improve signal quality of the apparatus.
Conclusion
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/DEORAM PERSAUD/ Primary Examiner, Art Unit 2882
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