DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
I. REJECTIONS BASED ON DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 26 of copending Application No. 16/904,597. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the instant application (19/008,669) are taught in claim 26 of the copending application (16/904,597). (Please note that as both the instant and copending applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and copending applications for the instant double patenting rejection)
II. ALLOWABLE SUBJET MATTER
Claim 25 is allowed.
Claims 7-8 and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
III. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Kim et al. (US Pub.: 2009/0154256), and Evans et al. (US Pub.: 2005/0015558).
As per claim 1, Akin teaches/suggests a memory chip comprising: a plurality of memory banks, each memory bank outputting or receiving a data set in parallel ([0018]-[0020]); an I/O data bus (e.g. associated data bus between sense amplifier (38) and SSN processor (40) in Fig. 2); and operating corresponding to the plurality of memory banks respectively; wherein the data set of one memory bank is transferred to the I/O data bus, or the data set is transferred from the I/O data bus to the one memory bank; operating accordingly between the I/O data bus and each memory bank (Fig. 2; and [0010]-[0020]).
Akin does not teach the memory chip comprising:
a plurality of align circuits;
transferred to one corresponding align circuit which then simultaneously transfers the data set in parallel, or transferred to the one corresponding align circuit which then simultaneously transfers the data set in parallel;
wherein there is no parallel-to-serial circuit and serial-to-parallel circuit in memory.
Kim teaches/suggests a system comprising: simultaneously transfers the data set in parallel, or simultaneously transfers the data set in parallel (e.g. associated with data being parallel communicated across DQ-1 to DQ-n in Fig. 1) (Fig. 2; Fig. 4; and [0033]-[0040]).
Evans teaches/suggests a system comprising: a plurality of align circuits (e.g. associated with Fig. 5, ref. 263); transferred to one corresponding align circuit which then communicate accordingly, or transferred to the one corresponding align circuit which then communicate accordingly (e.g. associated with data being communicated across data interface (263) accordingly: [0053]-[0054]); wherein there is no parallel-to-serial circuit and serial-to-parallel circuit in memory (e.g. associated with embodiment where data is being parallelly, without serialization, communicated between memory controller and memory device; therefore, architecture would not have conversion circuit such as parallel-to-serial circuit and serial-to-parallel circuit: Fig. 4-5; [0006]; [0051]) (Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; and [0151]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kim’s parallel bus architecture, and Evans’ data transferring architecture into Akin’s memory chip for the benefit of reducing detrimental impact (Kim, [0047]), and saving bandwidth (Evans, [0040]-[0041]) to obtain the invention as specified in claim 1.
As per claim 2, Akin, Kim, and Evans teach/suggest all the claimed features of claim 1, where Akin, Kim, and Evans further teach/suggest the memory chip comprising: wherein each align circuit comprises a first plurality of transceivers which connect to the I/O data bus through a direct sending/receiving bus, and a width of the I/O data bus equals to a width of the data set outputting from or receiving by each memory bank (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]).
As per claim 3, Akin, Kim, and Evans teach/suggest all the claimed features of claim 1, where Akin, Kim, and Evans further teach/suggest the memory chip comprising: wherein a plurality of the data set of the plurality of memory banks are outputted to the I/O data bus in a predetermined sequence (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]).
As per claim 4, Akin, Kim, and Evans teach/suggest all the claimed features of claim 3, where Akin, Kim, and Evans further teach/suggest the memory chip comprising: wherein the data set of each memory bank are shared with a common row address, and a column address for the data set of each memory bank are different from each other (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features as control path communicates address information.
As per claim 5, Akin, Kim, and Evans teach/suggest all the claimed features of claim 4, where Akin, Kim, and Evans further teach/suggest the memory chip comprising: wherein the column address for the data set of each memory bank is generated by the memory chip internally, or received from a memory controller external to the memory chip (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 6, Akin, Kim, and Evans teach/suggest all the claimed features of claim 3, where Akin, Kim, and Evans further teach/suggest the memory chip comprising: wherein the plurality of the data set of the plurality of memory banks are outputted to the I/O data bus within a bit switch cycle which comprises a plurality of phases, and the data set of each memory bank is outputted to the I/O data bus at a corresponding phase of the bit switch cycle (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Kim et al. (US Pub.: 2009/0154256), and Evans et al. (US Pub.: 2005/0015558) as applied to claim 1 above, and further in view of Kim et al. (US Pub.: 2005/0249003).
As per claim 9, Akin, Kim, and Evans teach/suggest all the claimed features of claim 1, where Akin, Kim, and Evans teach/suggest the memory chip further comprising: data lines; and a sensing amplifier coupled to the data lines, wherein the one memory bank operate accordingly, and being is between the one memory bank and the corresponding align circuit (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; and Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]), but Akin, Kim, and Evans do not teach the memory chip further comprising: a plurality set of sensing amplifiers, corresponds to one set of sensing amplifiers, and the corresponding set of sensing amplifiers is installed accordingly.
Kim et al. (US Pub.: 2005/0249003) teaches/suggests a system comprising: a plurality set of sensing amplifiers (e.g. associated with IOSA in Fig. 2; and IOSA (210)-(280) and (310)-(380) in Fig. 4), corresponds to one set of sensing amplifiers, and the corresponding set of sensing amplifiers is installed accordingly (Fig. 2; Fig. 4; and [0033]-[0040]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kim’s sense amplifier architecture into Akin, Kim, and Evans’ memory chip for the benefit of providing high-speed data transfer with decreased cell area (Kim et al. (US Pub.: 2005/0249003), [0024]) to obtain the invention as specified in claim 9.
As per claim 10, Akin, Kim et al. (US Pub.: 2009/0154256), Evans and Kim et al. (US Pub.: 2005/0249003) teach/suggest all the claimed features of claim 9, where Akin, Kim et al. (US Pub.: 2009/0154256), Evans and Kim et al. (US Pub.: 2005/0249003) further teach/suggest the memory chip comprising: the plurality of memory banks comprise a first memory bank and a second memory bank; the plurality set of sensing amplifiers comprise a first set of sensing amplifiers coupled to the data lines and a second set of sensing amplifiers coupled to the data lines; the first set of sensing amplifiers corresponds to the first memory bank, and a first data set is simultaneously transferred between the first set of sensing amplifiers and the I/O data bus in parallel through an align circuit corresponding to the first memory bank; the second set of sensing amplifiers corresponds to the second memory bank, and a second data set is simultaneously transferred between the second set of sensing amplifiers and the I/O data bus in parallel through another align circuit corresponding to the second memory bank; a width of the I/O data bus equals to a width of the first data set and a width of the second data set (Akin, Fig. 2; [0010]-[0020]; Kim et al. (US Pub.: 2009/0154256), Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim et al. (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0033]-[0040]), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 11, Akin, Kim et al. (US Pub.: 2009/0154256), Evans and Kim et al. (US Pub.: 2005/0249003) teach/suggest all the claimed features of claim 10, where Akin, Kim et al. (US Pub.: 2009/0154256), Evans and Kim et al. (US Pub.: 2005/0249003) further teach/suggest the memory chip comprising: wherein a width of a Dfi (DDR PHY Interface) bus of a physical layer circuit of a logic circuit equals to a sum of the width of the first data set and the width of the second data set, wherein the Dfi bus is coupled between a controller within the logic circuit and the physical layer circuit, the controller is further coupled to an AXI (Advanced extensible Interface) bus outside the logic circuit, and the logic circuit is coupled to the I/O data bus of the memory chip (Akin, Fig. 2; [0010]-[0020]; Kim et al. (US Pub.: 2009/0154256), Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim et al. (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0033]-[0040]), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 12, Akin, Kim et al. (US Pub.: 2009/0154256), Evans and Kim et al. (US Pub.: 2005/0249003) teach/suggest all the claimed features of claim 10, where Akin, Kim et al. (US Pub.: 2009/0154256), Evans and Kim et al. (US Pub.: 2005/0249003) further teach/suggest the memory chip further comprising: bit lines; a third set of sensing amplifiers coupled to the bit lines and configured between the first memory bank and the first set of sensing amplifiers; and a fourth set of sensing amplifiers coupled to the bit lines and configured between the second memory bank and the second set of sensing amplifiers (Akin, Fig. 2; [0010]-[0020]; Kim et al. (US Pub.: 2009/0154256), Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim et al. (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0033]-[0040]), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 13, Akin, Kim et al. (US Pub.: 2009/0154256), Evans and Kim et al. (US Pub.: 2005/0249003) teach/suggest all the claimed features of claim 12, where Akin, Kim et al. (US Pub.: 2009/0154256), Evans and Kim et al. (US Pub.: 2005/0249003) further teach/suggest the memory chip further comprising: a first bit switch set between the first set of sensing amplifiers and the third set of sensing amplifiers; and a second bit switch set between the second set of sensing amplifiers and the fourth set of sensing amplifiers (Akin, Fig. 2; [0010]-[0020]; Kim et al. (US Pub.: 2009/0154256), Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Kim et al. (US Pub.: 2005/0249003), Fig. 2; Fig. 4; [0033]-[0040]), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
Claims 14-22 are rejected under 35 U.S.C. 103 as being unpatentable over Akin et al. (US Pub.: 2019/0005376) in view of Kim et al. (US Pub.: 2009/0154256), Evans et al. (US Pub.: 2005/0015558) and Gaskins et al. (US Patent 5,261,068).
As per claim 14, Akin teaches/suggests a memory chip comprising: a first memory chip comprising: a first plurality of memory banks, each first memory bank outputting or receiving a data set in parallel ([0018]-[0020]); an I/O data bus (e.g. associated data bus between sense amplifier (38) and SSN processor (40) in Fig. 2); and operating corresponding to the plurality of memory banks respectively; wherein the data set of one first memory bank is transferred to the I/O data bus, or the data set is transferred from the I/O data bus to the one first memory bank; operating accordingly between the I/O data bus and each memory bank; and being external to and electrically connected to the I/O data bus of the first memory chip (Fig. 2; and [0010]-[0020]).
Akin does not teach the memory chip comprising:
a plurality of align circuits;
transferred to one corresponding align circuit which then simultaneously transfers the data set in parallel, or transferred to the one corresponding align circuit which then simultaneously transfers the data set in parallel;
wherein there is no parallel-to-serial circuit and serial-to-parallel circuit in memory; and
a logic circuit with a physical layer circuit, wherein the logic circuit is external, and a parallel-to-serial circuit and a serial-to-parallel circuit are located within the physical layer circuit.
Kim teaches/suggests a system comprising: simultaneously transfers the data set in parallel, or simultaneously transfers the data set in parallel (e.g. associated with data being parallel communicated across DQ-1 to DQ-n in Fig. 1) (Fig. 2; Fig. 4; and [0033]-[0040]).
Evans teaches/suggests a system comprising: a plurality of align circuits (e.g. associated with Fig. 5, ref. 263); transferred to one corresponding align circuit which then communicate accordingly, or transferred to the one corresponding align circuit which then communicate accordingly (e.g. associated with data being communicated across data interface (263) accordingly: [0053]-[0054]); wherein there is no parallel-to-serial circuit and serial-to-parallel circuit in memory (e.g. associated with embodiment where data is being parallelly, without serialization, communicated between memory controller and memory device; therefore, architecture would not have conversion circuit such as parallel-to-serial circuit and serial-to-parallel circuit: Fig. 4-5; [0006]; [0051]) (Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; and [0151]).
Gaskins teaches/suggests a system comprising: a logic circuit with a physical layer circuit, wherein the logic circuit is external, and a parallel-to-serial circuit and a serial-to-parallel circuit are located within the physical layer circuit (e.g. associated with interleave controller (24a) being external to memory banks (26b, 26c) that receives parallel data from memory banks (26b, 26c) for serially forwarding to data/ECC controller (18), and that receives serially from data/ECC controller (18) for parallelly forwarding to memory banks (26b, 26c) in Fig. 2) (Fig. 2-3; and col. 6, l. 64 to col. 9, l. 52).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kim’s parallel bus architecture, Evans’ data transferring architecture, and Gaskins’ interleaving architecture into Akin’s memory chip for the benefit of reducing detrimental impact (Kim, [0047]), saving bandwidth (Evans, [0040]-[0041]), and overlapping reading operations (Gaskins, col. 12, ll. 20-26) to obtain the invention as specified in claim 14.
As per claim 15, Akin, Kim, Evans and Gaskins teach/suggest all the claimed features of claim 14, where Akin, Kim, Evans and Gaskins further teach/suggest the memory system comprising: wherein the physical layer circuit further comprises a second plurality of transceivers electrically connected to the parallel-to-serial circuit and the serial-to-parallel circuit (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Gaskins, Fig. 2-3; col. 6, l. 64 to col. 9, l. 52), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 16, Akin, Kim, Evans and Gaskins teach/suggest all the claimed features of claim 15, where Akin, Kim, Evans and Gaskins further teach/suggest the memory system comprising: wherein the first plurality of memory banks comprises 2N banks, N is an integer not less than 1, and the parallel-to-serial circuit is a 2N:1 parallel-to-serial circuit, and the serial-to-parallel circuit is a 1: 2N serial-to-parallel circuit (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Gaskins, Fig. 2-3; col. 6, l. 64 to col. 9, l. 52), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 17, Akin, Kim, Evans and Gaskins teach/suggest all the claimed features of claim 15, where Akin, Kim, Evans and Gaskins further teach/suggest the memory system comprising: wherein a Dfi bus of the physical layer circuit equals to a sum of the width of the data set of each first memory bank of the first memory chip, wherein the Dfi bus is coupled between a controller within the logic circuit and the physical layer circuit (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Gaskins, Fig. 2-3; col. 6, l. 64 to col. 9, l. 52), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 18, Akin, Kim, Evans and Gaskins teach/suggest all the claimed features of claim 14, where Akin, Kim, Evans and Gaskins further teach/suggest the memory system comprising: wherein each align circuit of the first memory chip comprises a first plurality of transceivers which connect to the I/O data bus through a direct sending/receiving bus, and a width of the I/O data bus equals to a width of the data set outputting from or receiving by each first memory bank (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Gaskins, Fig. 2-3; col. 6, l. 64 to col. 9, l. 52), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 19, Akin, Kim, Evans and Gaskins teach/suggest all the claimed features of claim 14, where Akin, Kim, Evans and Gaskins further teach/suggest the memory system comprising: wherein a plurality of the data set of the first plurality of memory banks are outputted to the I/O data bus in a predetermined sequence (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Gaskins, Fig. 2-3; col. 6, l. 64 to col. 9, l. 52), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 20, Akin, Kim, Evans and Gaskins teach/suggest all the claimed features of claim 19, where Akin, Kim, Evans and Gaskins further teach/suggest the memory system comprising: wherein the data set of each first memory bank are shared with a common row address, and a column address for the data set of each first memory bank are different from each other (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Gaskins, Fig. 2-3; col. 6, l. 64 to col. 9, l. 52), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 21, Akin, Kim, Evans and Gaskins teach/suggest all the claimed features of claim 20, where Akin, Kim, Evans and Gaskins further teach/suggest the memory system comprising: wherein the column address for the data set of each first memory bank is generated by the first memory chip internally, or received from a memory controller external to the first memory chip (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Gaskins, Fig. 2-3; col. 6, l. 64 to col. 9, l. 52), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 22, Akin, Kim, Evans and Gaskins teach/suggest all the claimed features of claim 19, where Akin, Kim, Evans and Gaskins further teach/suggest the memory system comprising: wherein the plurality of the data set of the first plurality of memory banks are outputted to the I/O data bus within a bit switch cycle which comprises a plurality of phases, and the data set of each first memory bank is outputted to the I/O data bus at a corresponding phase of the bit switch cycle (Akin, Fig. 2; [0010]-[0020]; Kim, Fig. 2; Fig. 4; [0033]-[0040]; Evans, Fig. 4-5; [0006]; [0047]-[0054]; [0079]-[0080]; [0151]; and Gaskins, Fig. 2-3; col. 6, l. 64 to col. 9, l. 52), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features.
IV. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-25 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 June 12, 2026
Prosecution Insights