DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim(s) 1 has been cancelled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 11 from which the present claim depends and claim 8 from which claim 11 depends are explicitly clear that the operation involved is a data write to store in a memory device; at least writeback operation in claim 11, and “operations that writeback, to a memory array and after sense operations, the write data received via the data interface” in claim 8; claim 12 seems to make an attempt to change the scope of the previously disclosed write operations; it now requires, opposite to previous claims, “whether data to be written back is no longer going to be stored by the memory device.” If data is expressly defined to be written back, can it be not stored by the memory device? The claim is found indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4-6, 8-9, 11, 13-14, 16, 18 an 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 8873321 to Katoch (“Katoch”) in view of U.S. Patent/Publication No. 10803942 to Jung et al. (“Jung”).
As to claim 2, while Katoch teaches substantially the invention, including: a boosted bitline voltage to be used by the memory device during writeback operations (As found in at least Column 6, lines 57-62, Column 7, lines 5-7 and at least FIG. 4),
Katoch may not expressly include teachings of a controller, comprising: a command interface to communicate with a memory device, the command interface to write a first value to a register of the memory device that indicates a boosted bitline voltage; a data interface to receive data stored by the memory device using the boosted bitline voltage.
Yet, a memory controller having a memory interface that communicates with said memory is well-known and well-understood in the art (As such, for example, FIG. 17 of Jung teaches such memory controller 1720 interfacing and communicating with a memory 1718); additionally, the teachings of Jung include data interface to receive data stored by the memory device using the boosted bitline voltage (As found in at least FIG. 17: data stored in memory 1718 is received by interface (bi-directional bus)).
Moreover, Jung also teaches a boosted bitline voltage to be used by the memory device during writeback operations (As found in at least Column 18, lines 35-39; in short, higher voltage (boosted) write-back generates a current that flows from bit line to source line).
Katoch and Jung are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having bit line boosted voltages.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Katoch as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Jung also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: in the relevant art write-back operations provide: reduction of write latency and lower memory traffic by grouping multiple changes together. This is further accentuated by the use of bit line higher voltages.
Therefore, it would have been obvious to combine Katoch with Jung to make the above modification.
As to claim 4, Katoch as modified teaches wherein the controller selects the first value based on a use for the data associated with the writeback operations (the operations in the teachings of Katoch involve a writeback operation and the voltage used, as found in Jung, is in consideration of a memory controller and interface).
As to claim 5, as found in at least Katoch, wherein the command interface is to write a second value to the register of the memory device that indicates a second bitline voltage that is equal to a digital logic supply voltage is to be used by the memory device during writeback operations (As found in at least FIG. 2, bi lines are at a second value equal to supply voltage VDD; contrast this with FIG. 4).
As to claim 6, Katoch teaches wherein the command interface is to transmit a command with an indicator that the memory device is to use a bitline voltage that is equal to a digital logic supply voltage during writeback operations (As found in at least FIG. 2 and at least Column 6, lines 57-60: note bit line voltage at supply VDD).
As to claim 8, see rejection to at least claim 2; moreover, at least Katoch teaches “In some embodiments, a write back occurs after reading;” reading involves data sensing, as well-known and well-understood this is in the relevant art.
As to claim 9, Katoch teaches wherein the sense operations are to be performed using a second bitline voltage that is less than the first bitline voltage (As found in at least FIG. 1 and at least Column 2, lines 47-59; in short, in a sensing operation, bit lines are at VDD).
As to claim(s) 11 and 13, see rejection to at least claim 6.
As to claim 14, a writeback operation is a write operation.
As to claim 16, see rejection to at least claim 2; moreover, the method is inherently taught by the apparatus.
As to claim 18, Katoch teaches based on a use for the data associated with the writeback operations, selecting the first value (The use is a write operation).
As to claim 19, see rejection to at least claim 5.
As to claim 20, see rejection to at least claim 6.
Claim(s) 3, 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 8873321 to Katoch (“Katoch”) in view of U.S. Patent/Publication No. 10803942 to Jung et al. (“Jung”), and further in view of US 20200265889 to Hwang (“Hwang”).
As to claim 3, while Katoch as modified teaches a memory controller, at least Hwang, relevantly and complementarily, teaches wherein the controller selects the first value based on a temperature indicator associated with the memory device (As found in at least FIG. 4 and at least [0044]; in short, at a first value temperature bit line voltage is one, at a different value temperature bit line voltage is a second one; also see at least FIG. 1: controller generated command/signals responding to temperature sensor).
Katoch as modified and Hwang are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having bit line boosted voltages.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Katoch as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Hwang also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: in the relevant art write-back operations provide: semiconductor devices, including memory, are affected by at least process, temperature and voltage. A system that comprises mechanisms to address differences in these areas is advantageous.
Therefore, it would have been obvious to combine Katoch as modified with Hwang to make the above modification.
As to claim 10, see rejection to at least claim 3.
As to claim 17, see rejection to at least claim 3.
Claim(s) 7, 15 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 8873321 to Katoch (“Katoch”) in view of U.S. Patent/Publication No. 10803942 to Jung et al. (“Jung”), and further in view of US 10811078 to Cha et al. (“Cha”).
As to claim 7, at least Cha teaches wherein the command is associated with a refresh operation (As found in at least Column 13, lines 53-59: in a refresh operation, a write back operation is performed).
Katoch as modified and Cha are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having bit line boosted voltages.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Katoch as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Cha also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: as found in the teachings of Cha a write back operation may be involved in a refresh operation to correct error bits.
Therefore, it would have been obvious to combine Katoch as modified with Cha to make the above modification.
As to claim 15, see rejection to at least claim 7.
As to claim 21, see rejection to at least claim 7.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
At least Claim(s) 1, 8 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim(s) 1, 8 and 15 of U.S. Patent No. 12217784. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are obviated by the patented claims. A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over (in a non-statutory double patent rejection) the earlier claim. In re Lonqi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Bercl, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). Ely Lilly and Co. v Bar Laboratories, Inc., United States Court of Appeals for the Federal Circuit, on petition for rehearing en banc (decided: May 30, 2001).The instant claims are obviated by the patented claims; the patent and the application claim obvious common subject matter: a memory controller, comprising, in brief and saliently: writeback operations that may make use of bit line voltages at a boosted level and/or at a digital supply voltage level.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights