CTNF 19/011,055 CTNF 91558 DETAILED ACTION The action is responsive to the following communications: the Application filed January 06, 2025 and the information disclosure statement (IDS) filed January 06, 2025. This application is a CON of 17/407,875 filed August 20, 2021. Claims 1-20 are pending. Claims 1, 9 and 15 are independent. Notice of Pre-AIA or AIA Status The present application is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on January 06, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Independent claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over independent claims 1-20 of US Patent No. 12,190,927. Although the claims at issue are not identical, they are not patentably distinct from each other. Instant Application US Patent 12,190,927 Comment Claim 1. A method for operating a memory device, the method comprising: applying a word line voltage to a selected word line; applying a bit line voltage to a selected bit line; applying a first bias voltage to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line except a memory cell connected to both the selected bit line and the selected word line, the first bias voltage being less than 0 volt; and applying a second bias voltage to a gate of a reference memory cell transistor of a reference circuit, wherein the second bias voltage is greater than a supply voltage of the memory device. Claim 1. A method for operating a memory device, the method comprising: decoding a first address to select a bit line of a memory device; decoding a second address to select a word line of the memory device; applying a word line voltage to the selected word line; applying a bit line voltage to the selected bit line; applying a first bias voltage to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line except a memory cell connected to both the selected bit line and the selected word line, the first bias voltage being different than the word line voltage applied to the selected word line, wherein applying the first bias voltage comprises applying the first bias voltage that is less than 0 volt; and applying a second bias voltage to a gate of a reference memory cell transistor of a reference circuit, wherein the second bias voltage is greater than a supply voltage of the memory device. Note footnote 1 Allowable Subject Matter Claims 1-20 are rejected but would be allowable if overcoming nonstatutory double patenting as indicated above rejection. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The Applicant claims a semiconductor memory device (e.g., MRAM) and a method for operating the memory device with a bias circuit during read operation. Regarding independent claims 1, 9 and 15, after completing a thorough search, the closest reference to Yoon et al. (US 2009/0180315) disclose selectively applying negative voltage to word lines during memory device read operation. Claims 2-8, 10-14 and 16-20 are allowed due to claim dependency . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUNG IL CHO/Primary Examiner, Art Unit 2825 Application/Control Number: 19/011,055 Page 2 Art Unit: 2825 Application/Control Number: 19/011,055 Page 3 Art Unit: 2825 Application/Control Number: 19/011,055 Page 4 Art Unit: 2825 Application/Control Number: 19/011,055 Page 5 Art Unit: 2825 Application/Control Number: 19/011,055 Page 6 Art Unit: 2825 1 Re independent claims 1, 9 and 15 , claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
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