DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on January 6, 2025 has been considered by the examiner.
Priority
The present application, 19/011147, is a continuation of Application 18/298045, filed on April 10, 2023, which is a continuation of Application 17/359994, filed on June 28, 2021, which is a continuation of Application 16/869856, filed on May 8, 2020. The claim for priority through this chain is acknowledged as properly supported under 35 U.S.C. § 120.
Specification
The abstract of the disclosure is objected to because it exceeds 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
¶10 ‘Flow Chat’
¶31 Delay circuit 528 identified as 258
Appropriate correction is required.
Drawings
The drawings are objected to because:
Regarding Figure 5: The second delay circuit is labeled 528 but referenced as 258 in the specification at ¶31. Appropriate correction is required.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. in view of US 12190945 B2:
Claim
19/011147
Claim
US 12190945 B2
1
A random number generator (RNG), comprising:
1
during an RNG phase
1
a memory cell array including a plurality of bit cells, each of the plurality of bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively;
1
a memory cell array including a plurality of bit cells coupled to the bit lines and the word lines
1
a power supply terminal coupled to the memory cell array and configured to selectively provide a first voltage level to the memory cell array and
1
a power supply terminal coupled to the memory cell array;
1
a second voltage level to the memory cell array, wherein the second voltage level is lower than the first voltage level; and
3
precharge the bit lines to a second voltage level lower than the first voltage level.
1
a control circuit controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the control circuit is configured to:
1
a controller coupled to the word lines and the bit lines
1
during a static random access memory (SRAM) phase, operate the memory cell array at the first voltage level;
2
during an SRAM phase, operate the memory cell at a first voltage level
1
during an RNG phase, precharge the plurality of bit lines to the second voltage level,
1
during an RNG phase, precharge the bit lines
1
initiate a word line glitch, and
2
during the RNG phase, initiate a word line glitch.
1
determine initial logic states of the plurality of bit cells to generate at least one random number.
1
determine the initial logic states of the plurality of bit cells to generate a random number.
2
The RNG of claim 1, wherein to initiate the word line glitch comprises to feed a shutdown signal to a clamp transistor after a delay period, wherein the clamp transistor is configured to pull a decode signal or the word line signals to ground in response to the shutdown signal.
6
The memory device of claim 4, further comprising: a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period.
3
The RNG of claim 1, wherein the control circuit is configured to initiate the RNG phase by feeding a shutdown signal to a header switch connected to the memory cell array via the power supply terminal.
15
applying the shutdown signal at a first time point to a header switch configured to apply the first voltage level to the memory cell array in response to the shutdown signal.
4
The RNG of claim 3, wherein:
1
during an RNG phase
4
the shutdown signal is fed to the header switch at a first time; and
16
applying the shutdown signal to a first clamp switch at the first time point to hold an address decode signal at a first signal level
4
to initiate the word line glitch comprises to feed the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
8
a second delay circuit coupled to the input terminal and configured to delay the shutdown signal by a second delay period; and wherein the second clamp switch is configured to pull the word line signal to the ground voltage level in response to the delayed shutdown signal delayed by the second delay period.
5
The RNG of claim 3, wherein the shutdown signal is further fed to a leakage transistor connected between the header switch and a ground voltage terminal, wherein the leakage transistor is configured to provide a path to drain leakage current of the header switch.
5
a leakage transistor connected between the header switch and a ground voltage level, wherein the leakage transistor is configured to be turned on in response to the first state of the shutdown signal.
6
The RNG of claim 1, wherein the control circuit is further configured to cycle the memory cell array for a plurality of power loops before determining the initial logic states of the plurality of bit cells.
10
wherein the controller is configured to power the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.
7
The RNG of claim 1, wherein the second voltage level is between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for the bit line signals.
13
precharging the plurality of bit lines to a second voltage level lower than the first voltage level during a random number generator (RNG) phase during which the random number is generated.
8
A memory device, comprising:
8
a memory cell array including a plurality of bit cells, each of the plurality of bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively;
1
a memory cell array including a plurality of bit cells coupled to the bit lines and the word lines
8
a power supply terminal coupled to the memory cell array and
1
a power supply terminal coupled to the memory cell array;
8
configured to selectively provide a first voltage level to the memory cell array and a second voltage level to the memory cell array, wherein the second voltage level is lower than the first voltage level; and
3
precharge the bit lines to a second voltage level lower than the first voltage level.
8
a control circuit controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the control circuit is configured to:
1
a controller coupled to the word lines and the bit lines
8
during a static random access memory (SRAM) phase, operate the memory cell array at the first voltage level;
2
during an SRAM phase, operate the memory cell at a first voltage level
8
during an RNG phase, precharge the plurality of bit lines to the second voltage level,
1
during an RNG phase, precharge the bit lines
8
initiate a word line glitch, and
2
during the RNG phase, initiate a word line glitch.
8
determine initial logic states of the plurality of bit cells to generate at least one random number.
1
determine the initial logic states of the plurality of bit cells to generate a random number.
9
The memory device of claim 8, wherein to initiate the word line glitch comprises to feed a shutdown signal to a clamp transistor after a delay period, wherein the clamp transistor is configured to pull a decode signal or the word line signals to ground in response to the shutdown signal.
6
The memory device of claim 4, further comprising: a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period.
10
The memory device of claim 8, wherein the control circuit is configured to initiate the RNG phase by feeding a shutdown signal to a header switch connected to the memory cell array via the power supply terminal.
15
applying the shutdown signal at a first time point to a header switch configured to apply the first voltage level to the memory cell array in response to the shutdown signal.
11
The memory device of claim 10, wherein,
1
during an RNG phase
11
when the shutdown signal is fed to the header switch at a first time,
16
applying the shutdown signal to a first clamp switch at the first time point to hold an address decode signal at a first signal level
11
to initiate the word line glitch comprises to feed the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
8
a second delay circuit coupled to the input terminal and configured to delay the shutdown signal by a second delay period; and wherein the second clamp switch is configured to pull the word line signal to the ground voltage level in response to the delayed shutdown signal delayed by the second delay period.
12
The memory device of claim 10, wherein the shutdown signal is further fed to a leakage transistor connected between the header switch and a ground voltage terminal, wherein the leakage transistor is configured to provide a path to drain leakage current of the header switch.
5
a leakage transistor connected between the header switch and a ground voltage level, wherein the leakage transistor is configured to be turned on in response to the first state of the shutdown signal.
13
The memory device of claim 8, wherein the control circuit is further configured to cycle the memory cell array for a plurality of power loops before determining the initial logic states of the plurality of bit cells.
10
wherein the controller is configured to power the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.
14
The memory device of claim 8, wherein the second voltage level is between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for the bit line signals.
13
precharging the plurality of bit lines to a second voltage level lower than the first voltage level during a random number generator (RNG) phase during which the random number is generated.
15
A method, comprising:
18
A method, comprising:
15
toggling a shutdown signal supplied to a memory cell array from logical high to logical low,
18
receiving a shutdown signal; in response to the shutdown signal,
15
the memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines;
18
the memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines;
15
during a random number generator (RNG) phase:
18
during a random number generator (RNG) phase
15
precharging the plurality of bit lines to a voltage level between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for bit line signals;
18
precharging the bit lines to a second voltage level lower than the first voltage level
15
initiating a word line glitch; and
2
initiate a word line glitch.
15
generating a random number based on an initial state of each of the plurality of bit cells.
18
determining an initial state of the bit cells during the RNG phase
16
The method of claim 15, further comprising applying a second voltage level to the memory cell array at a static random access memory (SRAM) phase after the RNG phase, wherein the second voltage level is higher than the voltage level.
2
during an SRAM phase, operate the memory cell at a first voltage level
17
The method of claim 15, wherein initiating the word line glitch comprises feeding the shutdown signal to a clamp transistor after a delay period, wherein the clamp transistor is configured to pull a decode signal or word line signals to ground in response to the shutdown signal being at logical low.
16
wherein initiating the word line glitch includes: applying a shutdown signal at a first time point to a header switch configured to apply the first voltage level to the memory cell array in response to the shutdown signal;
18
The method of claim 15, wherein, when toggling the shutdown signal at a first time, initiating the word line glitch comprises feeding the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
16
applying the shutdown signal to a first clamp switch at the first time point to hold an address decode signal at a first signal level; and applying the shutdown signal to a second clamp switch at a second time point later than the first time point to hold a word line signal at the first signal level.
19
The method of claim 15, further comprising cycling the memory cell array for a plurality of power loops before generating the random number.
10
wherein the controller is configured to power the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.
20
The method of claim 15, further comprising feeding the shutdown signal to a leakage transistor configured to turn on when the shutdown signal is at logical low.
20
The method of claim 19, further comprising turning on a leakage transistor in response to the shutdown signal.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. in view of US 11626157 B2 in view of US 2017/0301732 A1 to Danial Robert Shepard, et al. (hereafter Shepard):
Claim
19/011147
Claim
11626157
1
A random number generator (RNG), comprising:
1
during a random number generator (RNG) phase
1
a memory cell array including a plurality of bit cells, each of the plurality of bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively;
1
a memory cell array including a plurality of bit cells, each of the plurality of bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines,
1
a power supply terminal coupled to the memory cell array and
Inherent in voltage controlled circuit
1
configured to selectively provide a first voltage level to the memory cell array and
1
and operate as a memory cell at a first voltage level during a static random access memory (SRAM) phase
1
a second voltage level to the memory cell array, wherein the second voltage level is lower than the first voltage level; and
1
during the RNG phase, precharge the plurality of bit lines to a second voltage level,
1
a control circuit controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the control circuit is configured to:
1
and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines,
1
during a static random access memory (SRAM) phase, operate the memory cell array at the first voltage level;
1
and operate as a memory cell at a first voltage level during a static random access memory (SRAM) phase
1
during an RNG phase, precharge the plurality of bit lines to the second voltage level,
1
during the RNG phase, precharge the plurality of bit lines to a second voltage level,
1
initiate a word line glitch, and
A voltage glitch introduces noise into an SRAM system, Shepard, ¶[0036]
1
determine initial logic states of the plurality of bit cells to generate at least one random number.
1
determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.
2
The RNG of claim 1, wherein to initiate the word line glitch comprises to feed a shutdown signal to a clamp transistor after a delay period, wherein the clamp transistor is configured to pull a decode signal or the word line signals to ground in response to the shutdown signal.
4
a first delay circuit coupled to the input terminal and configured to delay the shutdown signal by a first delay period; and a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period.
3
The RNG of claim 1, wherein the control circuit is configured to initiate the RNG phase by feeding a shutdown signal to a header switch connected to the memory cell array via the power supply terminal.
2
an input terminal configured to receive a shutdown signal; and a header switch connected between the first voltage level and the memory cell array, wherein the header switch is configured to be turned off in response to a first state of the shutdown signal.
4
The RNG of claim 3, wherein:
4
the shutdown signal is fed to the header switch at a first time; and
2
wherein the header switch is configured to be turned off in response to a first state of the shutdown signal.
4
to initiate the word line glitch comprises to feed the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
4
configured to delay the shutdown signal by a first delay period; and a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period
5
The RNG of claim 3, wherein the shutdown signal is further fed to a leakage transistor connected between the header switch and a ground voltage terminal, wherein the leakage transistor is configured to provide a path to drain leakage current of the header switch.
3
a leakage transistor connected between the header switch and a ground voltage level, wherein the leakage transistor is configured to be turned on in response to the first state of the shutdown signal.
6
The RNG of claim 1, wherein the control circuit is further configured to cycle the memory cell array for a plurality of power loops before determining the initial logic states of the plurality of bit cells.
8
The memory device of claim 2, wherein the controller is configured to power the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.
7
The RNG of claim 1, wherein the second voltage level is between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for the bit line signals.
1
during the RNG phase, precharge the plurality of bit lines to a second voltage level (Note: if a bit line is pre-charged, it inherently must be pre-charged to a voltage different from Vdd)
8
A memory device, comprising:
8
a memory cell array including a plurality of bit cells
8
a memory cell array including a plurality of bit cells, each of the plurality of bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively;
8
a memory cell array including a plurality of bit cells, each of the plurality of bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively,
8
a power supply terminal coupled to the memory cell array and configured to selectively provide a first voltage level to the memory cell array and a second voltage level to the memory cell array, wherein the second voltage level is lower than the first voltage level; and
8
a power supply terminal coupled to the memory cell array and configured to provide a first voltage level to the memory cell array during a static random access memory (SRAM) phase and a second voltage level to the memory cell array during the RNG phase, wherein the second voltage level is lower than the first voltage level;
8
a control circuit controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the control circuit is configured to:
8
control circuit controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the control circuit is configured to:
8
during a static random access memory (SRAM) phase, operate the memory cell array at the first voltage level;
8
configured to provide a first voltage level to the memory cell array during a static random access memory (SRAM) phase
8
during an RNG phase, precharge the plurality of bit lines to the second voltage level, initiate a word line glitch, and determine initial logic states of the plurality of bit cells to generate at least one random number.
8
during the RNG phase, precharge the plurality of bit lines to the second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number.
9
The memory device of claim 8, wherein to initiate the word line glitch comprises to feed a shutdown signal to a clamp transistor after a delay period, wherein the clamp transistor is configured to pull a decode signal or the word line signals to ground in response to the shutdown signal.
10
an input terminal configured to receive a shutdown signal; a header switch connected between the power supply terminal and the memory cell array, the header switch responsive to the shutdown signal; a word line driver coupled to the memory cell array configured to output a word line signal to the memory cell array; a bit line driver coupled to the memory cell array; and a delay circuit connected between the input terminal and the word line driver, and configured to delay the output of the word line signal to the word line driver in response to the shutdown signal such that the shutdown signal is received by the header switch before the word line signal is received by memory array.
10
The memory device of claim 8, wherein the control circuit is configured to initiate the RNG phase by feeding a shutdown signal to a header switch connected to the memory cell array via the power supply terminal.
13
wherein the delay circuit includes a clamp transistor coupled to the delay circuit and configured to pull the word line signal to a ground voltage level in response to the shutdown signal.
11
The memory device of claim 10, wherein, when the shutdown signal is fed to the header switch at a first time, to initiate the word line glitch comprises to feed the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
10
a delay circuit connected between the input terminal and the word line driver, and configured to delay the output of the word line signal to the word line driver in response to the shutdown signal such that the shutdown signal is received by the header switch before the word line signal is received by memory array.
12
The memory device of claim 10, wherein the shutdown signal is further fed to a leakage transistor connected between the header switch and a ground voltage terminal, wherein the leakage transistor is configured to provide a path to drain leakage current of the header switch.
12
The RNG of claim 10, further comprising a leakage transistor connected between the header switch and a ground voltage terminal, wherein the leakage transistor is configured to be turned on in response to the shutdown signal.
13
The memory device of claim 8, wherein the control circuit is further configured to cycle the memory cell array for a plurality of power loops before determining the initial logic states of the plurality of bit cells.
15
wherein the control circuit is configured to power the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.
14
The memory device of claim 8, wherein the second voltage level is between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for the bit line signals.
9
during the RNG phase, precharge the plurality of bit lines to a second voltage level (Note: if a bit line is pre-charged, it inherently must be pre-charged to a voltage different from Vdd)
15
A method, comprising:
16
A method, comprising
15
toggling a shutdown signal supplied to a memory cell array from logical high to logical low, the memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines;
16
receiving a shutdown signal; in response to the shutdown signal, applying a first voltage level to a memory cell array, the memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines;
15
during a random number generator (RNG) phase:
16
during a random number generator (RNG) phase;
15
precharging the plurality of bit lines to a voltage level between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for bit line signals;
16
precharging the plurality of bit lines to a second voltage level lower than the first voltage level during a random number generator (RNG) phase;
15
initiating a word line glitch; and
A voltage glitch introduces noise into an SRAM system, Shepard, ¶[0036]
15
generating a random number based on an initial state of each of the plurality of bit cells.
16
determining an initial state of each of the plurality of bit cells during the RNG phase.
16
The method of claim 15, further comprising applying a second voltage level to the memory cell array at a static random access memory (SRAM) phase after the RNG phase, wherein the second voltage level is higher than the voltage level.
1
and operate as a memory cell at a first voltage level during a static random access memory (SRAM) phase
17
The method of claim 15, wherein initiating the word line glitch comprises feeding the shutdown signal to a clamp transistor after a delay period, wherein the clamp transistor is configured to pull a decode signal or word line signals to ground in response to the shutdown signal being at logical low.
10
a delay circuit connected between the input terminal and the word line driver, and configured to delay the output of the word line signal to the word line driver in response to the shutdown signal such that the shutdown signal is received by the header switch before the word line signal is received by memory array.
18
The method of claim 15, wherein, when toggling the shutdown signal at a first time, initiating the word line glitch comprises feeding the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
16
receiving a shutdown signal; in response to the shutdown signal, applying a first voltage level to a memory cell array, the memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines;
19
The method of claim 15, further comprising cycling the memory cell array for a plurality of power loops before generating the random number.
20
The method of claim 17, further comprising: powering the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.
20
The method of claim 15, further comprising feeding the shutdown signal to a leakage transistor configured to turn on when the shutdown signal is at logical low.
12
further comprising a leakage transistor connected between the header switch and a ground voltage terminal, wherein the leakage transistor is configured to be turned on in response to the shutdown signal.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. in view of US 11049555 B2:
Claim
19/011147
Claim
11049555
1
A random number generator (RNG), comprising:
9
A random number generator (RNG) comprising:
1
a memory cell array including a plurality of bit cells, each of the plurality of bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively;
9
a memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines,
1
a power supply terminal coupled to the memory cell array and configured to selectively provide a first voltage level to the memory cell array and
9
a power supply terminal coupled to the memory cell array and configured to provide a first voltage level to the memory cell array;
1
a second voltage level to the memory cell array, wherein the second voltage level is lower than the first voltage level; and
10
configured to control the bit line driver to precharge the plurality of bit lines to a second voltage level lower than the first voltage level.
1
a control circuit controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the control circuit is configured to:
10
a control circuit coupled to the word line driver and the bit line driver,
1
during a static random access memory (SRAM) phase, operate the memory cell array at the first voltage level;
1
the first voltage level being a voltage level for operating the memory cell array during an SRAM phase.
1
during an RNG phase, precharge the plurality of bit lines to the second voltage level, initiate a word line glitch, and determine initial logic states of the plurality of bit cells to generate at least one random number.
16
during a random number generator (RNG) phase; initiating a word line glitch during the RNG phase; and determining an initial state of the bit cells during the RNG phase.
2
The RNG of claim 1, wherein to initiate the word line glitch comprises to feed a shutdown signal to a clamp transistor after a delay period,
4
a first delay circuit coupled to the input terminal and configured to delay the shutdown signal by a first delay period; and a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period.
2
wherein the clamp transistor is configured to pull a decode signal or the word line signals to ground in response to the shutdown signal.
5
a second clamp transistor configured to pull the word line signal to the ground voltage level in response to the shutdown signal.
3
The RNG of claim 1, wherein the control circuit is configured to initiate the RNG phase by feeding a shutdown signal to a header switch connected to the memory cell array via the power supply terminal.
2
a header switch connected between the first voltage level and the memory cell array, wherein the header switch is configured to be turned off in response to a first state of the shutdown signal.
4
The RNG of claim 3, wherein:
4
the shutdown signal is fed to the header switch at a first time; and
4
a first delay circuit coupled to the input terminal and configured to delay the shutdown signal by a first delay period; and a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period.
4
to initiate the word line glitch comprises to feed the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
5
a second clamp transistor configured to pull the word line signal to the ground voltage level in response to the shutdown signal.
5
The RNG of claim 3, wherein the shutdown signal is further fed to a leakage transistor connected between the header switch and a ground voltage terminal, wherein the leakage transistor is configured to provide a path to drain leakage current of the header switch.
3
a leakage transistor connected between the header switch and a ground voltage level, wherein the leakage transistor is configured to be turned on in response to the first state of the shutdown signal.
6
The RNG of claim 1, wherein the control circuit is further configured to cycle the memory cell array for a plurality of power loops before determining the initial logic states of the plurality of bit cells.
8
wherein the controller is configured to power the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.
7
The RNG of claim 1, wherein the second voltage level is between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for the bit line signals.
1
during the RNG phase, precharge the plurality of bit lines to a second voltage level (Note: if a bit line is pre-charged, it inherently must be pre-charged to a voltage different from Vdd)
8
A memory device, comprising:
1
A memory device, comprising:
8
a memory cell array including a plurality of bit cells, each of the plurality of bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively;
1
a plurality of bit lines; a plurality of word lines; a memory cell array including a plurality of bit cells coupled to the bit lines and the word lines,
8
a power supply terminal coupled to the memory cell array and
1
a power supply terminal coupled to the memory cell array;
8
configured to selectively provide a first voltage level to the memory cell array and
1
the first voltage level being a voltage level for operating the memory cell array during an SRAM phase.
8
a second voltage level to the memory cell array, wherein the second voltage level is lower than the first voltage level; and
1
during a RNG phase, precharge the bit lines to a second voltage level lower than a first voltage level,
8
a control circuit controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the control circuit is configured to:
1
a controller coupled to the word lines and the bit lines, the controller configured to:
8
during a static random access memory (SRAM) phase, operate the memory cell array at the first voltage level;
1
the first voltage level being a voltage level for operating the memory cell array during an SRAM phase.
8
during an RNG phase, precharge the plurality of bit lines to the second voltage level, initiate a word line glitch, and determine initial logic states of the plurality of bit cells to generate at least one random number.
16
during a random number generator (RNG) phase; initiating a word line glitch during the RNG phase; and determining an initial state of the bit cells during the RNG phase.
9
The memory device of claim 8, wherein to initiate the word line glitch comprises to feed a shutdown signal to a clamp transistor after a delay period,
4
a first delay circuit coupled to the input terminal and configured to delay the shutdown signal by a first delay period; and a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period.
9
wherein the clamp transistor is configured to pull a decode signal or the word line signals to ground in response to the shutdown signal.
5
a second clamp transistor configured to pull the word line signal to the ground voltage level in response to the shutdown signal.
10
The memory device of claim 8, wherein the control circuit is configured to initiate the RNG phase by feeding a shutdown signal to a header switch connected to the memory cell array via the power supply terminal.
2
a header switch connected between the first voltage level and the memory cell array, wherein the header switch is configured to be turned off in response to a first state of the shutdown signal.
11
The memory device of claim 10, wherein, when the shutdown signal is fed to the header switch at a first time, to initiate the word line glitch comprises to feed the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
4
a first delay circuit coupled to the input terminal and configured to delay the shutdown signal by a first delay period; and a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period.
12
The memory device of claim 10, wherein the shutdown signal is further fed to a leakage transistor connected between the header switch and a ground voltage terminal, wherein the leakage transistor is configured to provide a path to drain leakage current of the header switch.
3
a leakage transistor connected between the header switch and a ground voltage level, wherein the leakage transistor is configured to be turned on in response to the first state of the shutdown signal.
13
The memory device of claim 8, wherein the control circuit is further configured to cycle the memory cell array for a plurality of power loops before determining the initial logic states of the plurality of bit cells.
8
wherein the controller is configured to power the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.
14
The memory device of claim 8, wherein the second voltage level is between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for the bit line signals.
1
during the RNG phase, precharge the plurality of bit lines to a second voltage level (Note: if a bit line is pre-charged, it inherently must be pre-charged to a voltage different from Vdd)
15
A method, comprising:
16
A method, comprising
15
toggling a shutdown signal supplied to a memory cell array from logical high to logical low, the memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines;
16
in response to the shutdown signal, applying a first voltage level to a memory array, the memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines;
15
during a random number generator (RNG) phase:
16
during a random number generator (RNG) phase;
15
precharging the plurality of bit lines to a voltage level between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for bit line signals;
16
precharging the bit lines to a second voltage level lower than the first voltage level during a random number generator (RNG) phase;
15
initiating a word line glitch; and
16
initiating a word line glitch
15
generating a random number based on an initial state of each of the plurality of bit cells.
16
determining an initial state of the bit cells during the RNG phase.
16
The method of claim 15, further comprising applying a second voltage level to the memory cell array at a static random access memory (SRAM) phase after the RNG phase, wherein the second voltage level is higher than the voltage level.
1
the first voltage level being a voltage level for operating the memory cell array during an SRAM phase.
17
The method of claim 15, wherein initiating the word line glitch comprises feeding the shutdown signal to a clamp transistor after a delay period,
4
a first delay circuit coupled to the input terminal and configured to delay the shutdown signal by a first delay period; and a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period.
17
wherein the clamp transistor is configured to pull a decode signal or word line signals to ground in response to the shutdown signal being at logical low.
5
a second clamp transistor configured to pull the word line signal to the ground voltage level in response to the shutdown signal.
18
The method of claim 15, wherein, when toggling the shutdown signal at a first time, initiating the word line glitch comprises feeding the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
4
a first delay circuit coupled to the input terminal and configured to delay the shutdown signal by a first delay period; and a first clamp transistor coupled to the first delay circuit and configured to pull the memory address signal to the ground voltage level in response to the shutdown signal delayed by the first delay period.
19
The method of claim 15, further comprising cycling the memory cell array for a plurality of power loops before generating the random number.
8
wherein the controller is configured to power the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.
20
The method of claim 15, further comprising feeding the shutdown signal to a leakage transistor configured to turn on when the shutdown signal is at logical low.
3
a leakage transistor connected between the header switch and a ground voltage level, wherein the leakage transistor is configured to be turned on in response to the first state of the shutdown signal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 6-8, 10, 13-16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over M. T. Rahman, D. Forte, Xiaoxiao Wang and M. Tehranipoor, "Enhancing noise sensitivity of embedded SRAMs for robust true random number generation in SoCs," 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), Yilan, Taiwan, 2016, pp. 1-6 (hereafter Rahman) in view of D. E. Holcomb, W. P. Burleson and K. Fu, "Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers," in IEEE Transactions on Computers, vol. 58, no. 9, pp. 1198-1210, Sept. 2009, doi: 10.1109/TC.2008.212. (hereafter Holcomb) and further in view of US 2017/0301732 A1 to Danial Robert Shepard, et al. (hereafter Shepard).
Regarding Independent Claim 1, Rahman discloses a random number generator (RNG), comprising:
a memory cell array including a plurality of bit cells (Disclosing a SRAM cell array: Rahman, Figure 1a),
each of the plurality of bit cells coupled to one of a plurality of bit lines (Disclosing the cells connected to bitlines: Rahman, Figure 1a) and one of a plurality of word lines (Disclosing the cells coupled to the word lines: Rahman, Figure 1a), respectively;
a power supply terminal (Disclosing a power supply terminal: Rahman, §III.B, ¶1)
coupled to the memory cell array (The power supply terminal coupled to the memory cell array: Rahman, §III.B, ¶1) and
configured to selectively provide
a first voltage level to the memory cell array (Power supply configured to exceed retention voltage: Rahman, §III.B, ¶1) and
a second voltage level to the memory cell array (Power supply configured to provide reduced voltage of retention voltage or less: Rahman, §III.B, ¶1),
wherein the second voltage level is lower than the first voltage level (The first voltage, exceeding retention voltage, exceeds the second voltage of retention voltage or less: Rahman, §III.B, ¶1); and
a control circuit controlling
bit line signals on the plurality of bit lines and word line signals on the plurality of word lines (SRAM cells being configured to retain data during conventional operation: Rahman, §III.A, ¶2),
wherein the control circuit is configured to:
during a static random access memory (SRAM) phase, operate the memory cell array at the first voltage level (SRAM cells being configured to retain data during conventional operation: Rahman, §III.A, ¶2);
during an RNG phase (RNG generation: Rahman, §III.B, ¶1)
precharge the plurality of bit lines to the second voltage level (Operating the SRAM cells at the reduced voltage during RNG phase: Rahman, §III.B, ¶2), and
determine initial logic states of the plurality of bit cells (Reading the random generated data of the cells: Rahman, §III.B, ¶2)
to generate at least one random number (Generating at least one random number: Rahman, §III.B, ¶2).
Rahman discloses operating SRAM cells at a low voltage as a Random Number Generator, but it recommends the use of specially designed SRAM cells that are unusually susceptible to noise (Rahman, §III.A, ¶5, and Rahman, Figure 1c). Rahman does not teach away from applying the same technique to standard SRAM cells, but states the benefits of the specialized cells. Holcomb, on the other hand, discloses a similar RNG using standard six-transistor SRAM cells. Specifically, Holcomb teaches that extending the duration a SRAM cell is held at a low voltage makes it unusually susceptible to noise (At a low voltage supply, SRAM cells become highly susceptible to noise: Holcomb, §6.1, ¶1). Applicant is expressly attempting to increase the static noise margin (Specification, ¶[0027]). It would have been obvious to one having ordinary skill in the art before the effective filing date of this application, to use the reduced voltage of Rahman as a means of increasing the noise susceptibility recommended by Holcomb, with a reasonable expectation success.
That said, Holcomb only teaches the increased susceptibility of the circuit to external noise, it does not expressly suggest introducing a glitch. Shepard, however, expressly teaches the noise consequences of voltage glitches on SRAM cells (Shepard, ¶[0036]). Shepard teaches the consequences of a glitch specifically to teach away from them as they introduce noise into the circuit (Shepard, ¶[0036]). Introducing noise is specifically recommended by Holcomb, however (Holcomb, §6.1, ¶1). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to intentionally trigger a glitch (as in Shepard) to increase circuit noise (as recommended by Holcomb) in the voltage controlled RNG system of Rahman, with a reasonable expectation of success. All three applications are concerned with noise control in SRAM circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 3 and the substantially similar limitations of Claim 10, Rahman discloses the RNG of claim 1, wherein the control circuit is configured to
initiate the RNG phase by feeding a shutdown signal to a header switch connected to the memory cell array via the power supply terminal (Initiating the RNG process by initially reducing the bitline voltage by bitline gating: Rahman, Rahman, §III.B, ¶1).
Regarding Claim 6 and the substantially similar limitations of Claims 13 and 19, Holcomb discloses the RNG of claim 1, wherein the control circuit is further configured
to cycle the memory cell array for a plurality of power loops before determining the initial logic states of the plurality of bit cells (Recommending averaging results over multiple power-ups to properly identify randomness in cells: Holcomb, §3.2, ¶3-4).
Regarding Claim 7 and the substantially similar limitations of Claim 14, y discloses the RNG of claim 1, wherein
the second voltage level is between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for the bit line signals (The recommended RNG voltage being below retention voltage and above the shut-down voltage approaching Vss: Rahman, §III.B, ¶1).
Regarding Independent Claim 8, Rahman discloses a memory device, comprising:
a memory cell array including a plurality of bit cells (Disclosing a SRAM cell array: Rahman, Figure 1a),
each of the plurality of bit cells coupled to one of a plurality of bit lines (Disclosing the cells connected to bitlines: Rahman, Figure 1a) and one of a plurality of word lines (Disclosing the cells coupled to the word lines: Rahman, Figure 1a), respectively;
a power supply terminal (Disclosing a power supply terminal: Rahman, §III.B, ¶1)
coupled to the memory cell array (The power supply terminal coupled to the memory cell array: Rahman, §III.B, ¶1) and
configured to selectively provide
a first voltage level to the memory cell array (Power supply configured to exceed retention voltage: Rahman, §III.B, ¶1) and
a second voltage level to the memory cell array (Power supply configured to provide reduced voltage of retention voltage or less: Rahman, §III.B, ¶1),
wherein the second voltage level is lower than the first voltage level (The first voltage, exceeding retention voltage, exceeds the second voltage of retention voltage or less: Rahman, §III.B, ¶1); and
a control circuit controlling
bit line signals on the plurality of bit lines and word line signals on the plurality of word lines (SRAM cells being configured to retain data during conventional operation: Rahman, §III.A, ¶2),
wherein the control circuit is configured to:
during a static random access memory (SRAM) phase, operate the memory cell array at the first voltage level (SRAM cells being configured to retain data during conventional operation: Rahman, §III.A, ¶2);
during an RNG phase (RNG generation: Rahman, §III.B, ¶1)
precharge the plurality of bit lines to the second voltage level (Operating the SRAM cells at the reduced voltage during RNG phase: Rahman, §III.B, ¶2), and
determine initial logic states of the plurality of bit cells (Reading the random generated data of the cells: Rahman, §III.B, ¶2)
to generate at least one random number (Generating at least one random number: Rahman, §III.B, ¶2).
Rahman discloses operating SRAM cells at a low voltage as a Random Number Generator, but it recommends the use of specially designed SRAM cells that are unusually susceptible to noise (Rahman, §III.A, ¶5, and Rahman, Figure 1c). Rahman does not teach away from applying the same technique to standard SRAM cells, but states the benefits of the specialized cells. Holcomb, on the other hand, discloses a similar RNG using standard six-transistor SRAM cells. Specifically, Holcomb teaches that extending the duration a SRAM cell is held at a low voltage makes it unusually susceptible to noise (At a low voltage supply, SRAM cells become highly susceptible to noise: Holcomb, §6.1, ¶1). Applicant is expressly attempting to increase the static noise margin (Specification, ¶[0027]). It would have been obvious to one having ordinary skill in the art before the effective filing date of this application, to use the reduced voltage of Rahman as a means of increasing the noise susceptibility recommended by Holcomb, with a reasonable expectation success.
That said, Holcomb only teaches the increased susceptibility of the circuit to external noise, it does not expressly suggest introducing a glitch. Shepard, however, expressly teaches the noise consequences of voltage glitches on SRAM cells (Shepard, ¶[0036]). Shepard teaches the consequences of a glitch specifically to teach away from them as they introduce noise into the circuit (Shepard, ¶[0036]). Introducing noise is specifically recommended by Holcomb, however (Holcomb, §6.1, ¶1). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to intentionally trigger a glitch (as in Shepard) to increase circuit noise (as recommended by Holcomb) in the voltage controlled RNG system of Rahman, with a reasonable expectation of success. All three applications are concerned with noise control in SRAM circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 15, Rahman discloses a method, comprising:
toggling a shutdown signal supplied to a memory cell array from logical high to logical low (Initiating the RNG process by initially reducing the bitline voltage by bitline gating: Rahman, Rahman, §III.B, ¶1),
the memory cell array having a plurality of bit cells (Disclosing a SRAM cell array: Rahman, Figure 1a) coupled to a plurality of bit lines (Disclosing the cells connected to bitlines: Rahman, Figure 1a) and a plurality of word lines (Disclosing the cells coupled to the word lines: Rahman, Figure 1a);
during a random number generator (RNG) phase (RNG generation: Rahman, §III.B, ¶1):
precharging the plurality of bit lines to a voltage level (Operating the SRAM cells at the reduced voltage during RNG phase: Rahman, §III.B, ¶2) between a threshold voltage of a plurality of transistors in the plurality of bit cells and a voltage at drain (VDD) for bit line signals (The recommended RNG voltage being below retention voltage and above the shut-down voltage approaching Vss: Rahman, §III.B, ¶1);
initiating a word line glitch (At a low voltage supply, SRAM cells become highly susceptible to noise: Holcomb, §6.1, ¶1); and
generating a random number (Generating at least one random number: Rahman, §III.B, ¶2) based on an initial state of each of the plurality of bit cells (Reading the random generated data of the cells: Rahman, §III.B, ¶2).
Regarding Claim 16, Rahman discloses the method of claim 15, further comprising
applying a second voltage level (Power supply configured to exceed retention voltage: Rahman, §III.B, ¶1) to the memory cell array at a static random access memory (SRAM) phase (SRAM cells being configured to retain data during conventional operation: Rahman, §III.A, ¶2) after the RNG phase, wherein the second voltage level is higher than the voltage level (The second voltage, exceeding retention voltage, exceeds the first voltage of retention voltage or less: Rahman, §III.B, ¶1).
Claim(s) 5, 12, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over M. T. Rahman, D. Forte, Xiaoxiao Wang and M. Tehranipoor, "Enhancing noise sensitivity of embedded SRAMs for robust true random number generation in SoCs," 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), Yilan, Taiwan, 2016, pp. 1-6 (hereafter Rahman), D. E. Holcomb, W. P. Burleson and K. Fu, "Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers," in IEEE Transactions on Computers, vol. 58, no. 9, pp. 1198-1210, Sept. 2009, doi: 10.1109/TC.2008.212. (hereafter Holcomb), and US 2017/0301732 A1 to Danial Robert Shepard, et al. (hereafter Shepard) in view of US 2011/0292753 A1 to Kuoyuan (Peter) Hsu, et al. (hereafter Hsu).
Regarding Claim 5 and the substantially similar limitations of Claim 12, Rahman discloses the RNG of claim 3, but fails to disclose the further limitations of Claim 5. Hsu, however, discloses a SRAM memory array, wherein
the shutdown signal is further fed to a leakage transistor (Leakage transistor controlled by a standby signal: Hsu, Figure 1)
connected between the header switch and a ground voltage terminal (The leakage transistor connected between the header and Vss: Hsu, Figure 1),
wherein the leakage transistor is configured to provide a path to drain leakage current of the header switch (Inherent in the transistor being connected between the header and ground voltage).
Hsu teaches the implementation of a leakage transistor between the header control and ground allows for greater control of residual leakage current in the circuit (Hsu, ¶[0019]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the leakage transistor of Hsu with the RNG architecture of Rahman, with a reasonable expectation of success. Both inventions are well known in the field of SRAM memory array voltage control mechanisms and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 20, Rahman discloses the method of claim 15, but fails to disclose the further limitations of Claim 20. Hsu, however, discloses a SRAM circuit, further comprising
feeding the shutdown signal to a leakage transistor configured to turn on when the shutdown signal is at logical low (Leakage transistor controlled by a standby signal: Hsu, Figure 1).
Hsu teaches the implementation of a leakage transistor between the header control and ground allows for greater control of residual leakage current in the circuit (Hsu, ¶[0019]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the leakage transistor of Hsu with the RNG architecture of Rahman, with a reasonable expectation of success. Both inventions are well known in the field of SRAM memory array voltage control mechanisms and the combination of known inventions with predictable results is obvious and not patentable.
Allowable Subject Matter
Claim 2, 4, 9, 11, and 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2 and the substantially similar limitations of Claims 9 and 17, Rahman discloses the RNG of claim 1, but fails to disclose the mechanics of introducing a glitch via a shutdown signal to a clamp transistor. Specifically, wherein to initiate the word line glitch comprises to feed a shutdown signal to a clamp transistor after a delay period, wherein the clamp transistor is configured to pull a decode signal or the word line signals to ground in response to the shutdown signal.
Regarding Claim 4 and the substantially similar limitations of Claims 11 and 18, Rahman discloses the RNG of claim 3, but fails to disclose the mechanics of introducing a glitch via a shutdown signal to a clamp transistor. Specifically, wherein: the shutdown signal is fed to the header switch at a first time; and to initiate the word line glitch comprises to feed the shutdown signal to a clamp transistor after a delay period so the shutdown signal is fed to the clamp transistor at the first time or at a second time after the first time during the RNG phase.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2014/0241089 A1 to Lakshmikantha V. Holla, et al.: Disclosing a word line suppression circuit configured to maintain reduced voltage in a SRAM memory array specifically to increase the static noise margin of the circuit.
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/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824
/JEROME LEBOEUF/ Primary Examiner, Art Unit 2824 - 07/22/2026
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