DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 2-21 are pending and examined. Claim 1 has been cancelled.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12,230,355. Although the claims at issue are not identical, they are not patentably distinct from each other because both recite similar limitations of first, second, and third minimum time delay interval between memory banks of different bank clusters, memory banks of different bank groups of the same bank cluster, and memory banks of same bank group, respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,074,413 to Matsuoka (hereafter Matsuoka).
Regarding independent claim 10, Matsuoka teaches a controller, comprising:
circuitry to select a command issuance schedule for commands to be transmitted to a memory device, the command issuance schedule to meet a first delay interval between successive commands of a same type that are addressed to memory banks that are member of different bank groups (FIG. 1: memory controller 200 issues command PREA to perform write and pre-charge operations to all banks, see 5:37-53; FIG. 7: first minimum delay interval between required command CWI_B0 to BG0, BK0 and command CWI_B2 to BG1, BK0 is T12a-T12b, also see 5:37-53, wherein two BK0 belong to two different bank groups BG0 and BG1), the command issuance schedule to meet a second delay interval between successive commands of the same type that are addressed to memory banks that are members of a same bank group (FIG. 7: second minimum delay interval between command CWI_B0 to BG0,BK0 and command CWI_B2 to BG0, BK1 is T12a-T12c, wherein BK0 and BK1 belong to same bank group BG0); and
circuitry to transmit commands that follow the selected command issuance schedule to the memory device (FIG. 1: internal controller 120).
Regarding dependent claim 11, Matsuoka teaches wherein the selected command issuance schedule comprises commands that result in a plurality of rows of at least one memory bank of the memory device being open concurrently (because command PREA is issued to perform write and pre-charge operations to all banks).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-9, 12-14, 16-21 are rejected under 35 U.S.C. 103 as being unpatentable over US 7,765,359 to Kang et al. (hereafter Kang) in view Matsuoka.
Examiner’s note: Kang describes, in FIG. 3 and 4:7-5:3, a memory system comprising four flash memory chips 351-354, which are seen equivalent to recited bank group clusters. FIG. 4 and 5:4-18 describe each flash memory chip comprises k-th memory cell arrays, which are seen equivalent to recited bank group. Each memory cell array comprises a plurality of pages. Kang further describes, in FIG. 6 and 5:42-6:34, the data are written into four flash memory chips in an interleaving manner.
Matsuoka describes, in FIG. 1, a memory system comprises a memory chip 1, which is seen equivalent to a recited bank group cluster. The memory chip comprises two bank groups BG0 and BG1, which are also equivalent to recited bank groups. Each bank group comprises four memory banks BK0-BK3. Matsuoka also describes, in FIG. 7 and 5:37-53, the data are written into the memory chip in an interleaving manner.
Regarding independent claim 2, Kang teaches a controller (FIG. 3: control unit 340), comprising:
circuitry to issue operations to meet a first minimum time delay interval timing constraint between an issuance, to a memory device, of successive operations of a same type addressed to first memory banks of the memory device that are members of different bank groups clusters (delay between first page P1 of first memory array of CH1 and first page P2 of first memory array of CH2, see (1) and (2) annotated FIG. 6 below), and to issue operations to meet a second minimum time delay interval timing constraint between an issuance of successive operations of the same type which are addressed to memory pages of the memory device that are members of a first bank group cluster and also members of different bank groups of the first bank group cluster (delay between first page P1 of first memory array of CH1 and fifth page P5 of second memory array of CH1, see (1) and (3) in annotated FIG. 6 below).
Kang teaches issuing operations instead of issuing commands for the operations. Kang also does not explicitly teach fifth page P5 is first page of second memory array of the corresponding chip.
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Annotated FIG. 6
Matsuoka teaches circuitry to issue commands for operations to meet a first minimum time delay interval timing constraint between an issuance of successive commands of the same type which are addressed to memory banks of the memory device that are members of a first bank group cluster and also members of different bank groups of the first bank group cluster (FIG. 1: memory controller 200 issuing command PREA to perform write and pre-charge operations to all banks of the memory device, FIG. 7: first command minimum delay interval between command CWI_B0 to BG0, BK0 and command CWI_B1 to BG1, BK0 is T12a-T12b, wherein two BK0 belong to two different bank groups BG0 and BG1).
Since Kang and Matsuoka are both from the same field of endeavor, the purpose disclosed by Matsuoka would have been recognized in the pertinent art of Kang.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art:
to realize that in order to perform an operation on a corresponding address, a command should be issued to the memory chip for each operation as suggested in Matsuoka;
to incorporate the interleave operation between memory banks of the same memory chip, as suggested in Matsuoka, into each memory chip of Kang to maintain interleaving at the memory bank level for high-speed operation (see Kang, 2:66-3:3 and Matsuoka, 1:16-30).
Assuming each memory chip of Kang comprises eight memory arrays, same as eight memory banks of Matsuoka. Examiner proposes the following access sequence when memory system of Kang incorporate features of Matsuoka.
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Examiner’s Proposed Access Sequence
There appears the first minimum time delay between memory banks of same bank group and same bank cluster has a constant value of 8, the second minimum time delay between memory banks of different bank groups and same bank cluster has a constant value of 4, and the third minimum time delay between memory banks of different bank groups and different bank clusters has a constant value of 3. First, second, and third minimum time delay are not equal.
Regarding dependent claim 3, Kang teaches an inherent scheduling circuitry to determine a command issuance order that meets the first minimum time delay interval timing constraint (FIG. 6: inherent scheduling circuitry to generate delay signals as shown).
Regarding dependent claim 4, Matsuoka teaches wherein the scheduling circuitry is to further determine the command issuance order that meets the second minimum time delay interval timing constraint (see FIG. 4).
Regarding dependent claim 5, Matsuoka teaches wherein the controller is to also issue commands that meet a third minimum time delay interval timing constraint between an issuance of successive commands of the same type which are addressed to memory banks of the memory device that are members of a first bank group of the first bank group cluster (FIG. 7: delay interval between command CWI_B0 to BG0, BK0 and command CWI_B1 to BG0, BK1 is T12a-T12c, wherein both BK0 and BK1 belong to same bank group BG0).
Regarding dependent claims 6-7, see rejection applied to claim 2 above.
Regarding dependent claim 8, Matsuoka teaches wherein the command issuance order results in a plurality of rows of a memory bank of the first bank group of the first bank group cluster being open concurrently (because command PREA is issued to perform write and pre-charge operations to all banks).
Regarding dependent claim 9, Matsuoka teaches circuitry to associate respective indicators with a respective plurality of row address ranges of a memory bank of the first bank group of the first bank group cluster where the respective indicators are to be associated with each of the respective plurality of row address ranges being unavailable for opening a row (i.e. selecting a row of plurality of rows in response to the row address decoded by inherent row decoder).
Regarding dependent claim 12, Matsuoka doesn’t teach the recited limitations. However, Kang teaches a third delay interval between successive commands of the same type to a first open row of a memory bank and a second open row of the memory bank (see rejection applied to claim 2 above).
Regarding dependent claims 13-14, see rejection applied to claim 2 above.
Regarding independent claim 16, Kang teaches a method of operating a controller, comprising:
issuing, to a memory device, a first pair of successive operations of a same type to meet a first minimum time delay interval timing constraint between an issuance, to the memory device, of successive operations of the same type which are addressed to memory banks of the memory device that are members of different bank group clusters (delay between first page P1 of first memory array of CH1 and first page P2 of first memory array of CH2, see (1) and (2) in annotated FIG. 6 above); and
issuing, to the memory device, a second pair of successive operations of the same type to meet a second minimum time delay interval timing constraint between an issuance of successive operations of the same type which are addressed to memory pages of the memory device that are members of a first bank group cluster and are also members of different bank groups of the first bank group cluster (delay between first page P1 of first memory array of CH1 and fifth page P5 of second memory array of CH1, see (1) and (3) in annotated FIG. 6 above).
Kang teaches issuing operations instead of issuing commands for the operations. Kang also does not explicitly teach fifth page P5 is first page of second memory array of the corresponding chip.
Matsuoka teaches circuitry to issue commands for operations to meet a first minimum time delay interval timing constraint between an issuance of successive commands of the same type which are addressed to memory banks of the memory device that are members of a first bank group cluster and also members of different bank groups of the first bank group cluster (FIG. 1: memory controller 200 issuing command PREA to perform write and pre-charge operations to all banks of the memory device, FIG. 7: first command minimum delay interval between command CWI_B0 to BG0, BK0 and command CWI_B1 to BG1, BK0 is T12a-T12b, wherein two BK0 belong to two different bank groups BG0 and BG1).
Since Kang and Matsuoka are both from the same field of endeavor, the purpose disclosed by Matsuoka would have been recognized in the pertinent art of Kang.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art:
to realize that in order to perform an operation on a corresponding address, a command should be issued to the memory chip for each operation as suggested in Matsuoka;
to incorporate the interleave operation between memory banks of the same memory chip, as suggested in Matsuoka, into each memory chip of Kang to maintain interleaving at the memory bank level for high-speed operation (see Kang, 2:66-3:3 and Matsuoka, 1:16-30).
Regarding dependent claims 17-21, see rejections applied to claims 2-7 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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August 26, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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