Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Fardad (Patent Application Publication 2019/0131308) in view of Lee (Patent Application Publication 2012/0044734).
Claim 1. A device, comprising: a substrate (peripheral circuit area formed on a first substrate or lower deck, Fardad Fig 1); a first sense amplifier disposed on the substrate (sense amplifier circuitry included in the peripheral circuitry beneath the array, Fardad Figs 1, 3-5); a first memory array disposed above the first sense amplifier (memory array upper deck above the lower-deck peripheral circuitry, Fardad Fig 1. Sense amplifiers under memory core Figs 3-5); and a plurality of first conductive segments (multiple metal interconnect layers coupling the peripheral region to word-line and digit-line structures, Fardad Fig 1, 6-8), the plurality of first conductive segments disposed between the first memory array and the first sense amplifier (interconnecting layers between the lower-deck peripheral circuits and upper memory array, Fardad Figs 1 and 7) and configured to (configured to is functional language) electrically connect the first sense amplifier to a first bit line of the first memory array, but is silent with respect to extend alternately in a first direction and a second direction.
Lee discloses bit lines connected to sense amps using zigzag routing (Lee [0059]) for the purpose of allowing a bitline sense amp layout to be constructed even as memory cell and bit line pitch is reduces (Lee Fig 2-3, [0061], claim 2)
Since Fardad and Lee are both from the same field of endeavor (bitline and sense amp circuit in semiconductor memory), the purpose disclosed by Lee would have been recognized in the pertinent art of Fardad.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the zigzag connection taught by Lee in the circuit taught by Fardad for the purposes of allowing a bitline sense amp layout to be constructed even as memory cell and bit line pitch is reduced.
Claim 2. The device of claim 1, comprising: a word line driver disposed on the substrate next to the first sense amplifier in the first direction (sense amps and sub word line drivers located beneath the memory and arranged adjacent, staggered relative to one another, Fardad Fig 3-5); and a plurality of second conductive segments that extend alternately in the first direction and the second direction (Lee [0059-0061] Fig 2-3), the plurality of second conductive segments disposed between the first memory array and the word line driver (interconnect structure between the under array sub word line driver and the memory core word line, Fardad Fig 2, 5-8) and (configured to is functional language) electrically connect the word line driver to a word line of the first memory array (SWD 509 and word line 503, Fardad Fig 5).
Claim 3. The device of claim 2, wherein the first bit line of the first memory array (digit lines extending along one dimension of the memory core, Fardad Fig 3-8) is situated in the first direction of the first memory array and the word line of the first memory array is situated in the second direction of the first memory array (word lines externing transverse to the digit lines, Fardad Fig 3-8).
Claim 4. The device of claim 3, wherein the first bit line is connected to the first sense amplifier through a first conductive segment that extends in the second direction (multi direction zigzag bit line path connected to the sense amp, Lee [0059], Fig 2-3) and the word line is connected to the word line driver through a second conductive segment that extends in the first direction (transverse word line routing and under array SWD connection, Fardad Figs 5-8).
Claim 5. The device of claim 2, wherein the word line of the first memory array is situated in the first direction of the first memory array and the first bit line of the first memory array is situated in the second direction of the first memory array (orthogonal word line and digit line organization, Fardad Fig 3-8).
Claim 6. The device of claim 5, wherein the word line is connected to the word line driver through a second conductive segment that extends in the second direction (word line and sub word line driver conductive interconnection, Fardad, Fig 5-8) and the first bit line of the first memory array is connected to the first sense amplifier through a first conductive segment that extends in the first direction (zigzag bit line and sense amp connection including conductive portions extending in differing directions, Lee [0059], Fig 2-3).
Claims 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Fardad (Patent Application Publication 2019/0131308) in view of Lee (Patent Application Publication 2012/0044734), further in view of He (U.S. Patent Application 11024366).
Claim 7. Fardad teaches the device of claim 1, but is silent with respect to a second sense amplifier disposed on the substrate; a second memory array disposed above the second sense amplifier; and a plurality of third conductive segments that extend alternately in the first direction and the second direction, the plurality of third conductive segments disposed between the second memory array and the first sense amplifier and electrically connect the first sense amplifier to a second bit line of the second memory array.
He teaches a second sense amplifier disposed on the substrate (multiple banks of sense amplifiers associated with neighboring memory mats, He Fig 2-5); a second memory array disposed above the second sense amplifier (memory array mats associated with sense amp circuitry, He Fig 2-5); and a plurality of third conductive segments that extend alternately in the first direction and the second direction (zigzag conductive routing Lee [0059] Fig 2-3), the plurality of third conductive segments disposed between the second memory array and the first sense amplifier (sense amp bank connected with bit lines extending through an adjacent memory mat region, He Fig 2-5) and (configured to is functional language) electrically connect the first sense amplifier to a second bit line of the second memory array (sense amp banks coupled to respective bit lines of neighboring memory mats, He Fig 2-5) for the purpose of efficiently using memory cells of the edge memory array matt by avoiding bitlines and corresponding memory cells from being unused, providing greater memory density (He Col 5 lines 40-48, Fig 2).
Since Fardad, Lee and He are from the same field of endeavor (sense amps in semiconductor memory), the purpose disclosed by He would have been recognized in the pertinent art of Fardad and Lee.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the multiple sense amp and adjacent array connections taught by He in the memory taught by Fardad together with the zigzag routing taught by Lee for the purposes of efficiently using memory cells of the edge memory array matt by avoiding bitlines and corresponding memory cells from being unused, providing greater memory density.
Claim 8. The device of claim 7, comprising: a plurality of fourth conductive segments that extend alternately in the first direction and the second direction (zigzag conductive routing Lee [0059] Fig 2), the plurality of fourth conductive segments disposed between the second memory array and the second sense amplifier (sense amplifier bank positioned under the edge memory matt, He Fig 2) and (configured to is functional language) electrically connect the second sense amplifier to a third bit line of the second memory array (pairs of the bit line segments coupled to the sense amp bank positioned within the edged memory array mat, He Fig 2, Col 7 Lines 24-25).
Claim 9. The device of claim 8, comprising: a plurality of fifth conductive segments that extend alternately in the first direction and the second direction (zigzag conductive routing, Lee [0059] Fig 2), the plurality of fifth conductive segments disposed between the first memory array and the second sense amplifier and (configured to is functional language) electrically connect the second sense amplifier to a fourth bit line of the first memory array (sense amp banks coupled to bit lines associated with neighboring memory array mats, He Fig 2, Col 7 Lines 1-45).
Claim 10. The device of claim 1, wherein the first memory array has an array footprint that has a middle portion and a footprint boundary, and the first sense amplifier is situated near the footprint boundary of the array footprint (sense amp bank 220(2) adjacent the edge memory mat, He Fig 2 Col 7 lines 1-15, same motivation to combine as claim 7).
Claim 11. The device of claim 1, wherein the first memory array has an array footprint that has a middle portion and a footprint boundary, and the first sense amplifier is situated in the middle portion of the array footprint (sense amp bank within the edge memory mat, He Fig 2 col 7 lines 1-15, same motivation to combine as claim 7).
Claims 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Fardad (Patent Application Publication 2019/0131308) in view of Lee (Patent Application Publication 2012/0044734), further in view of He (U.S. Patent Application 11024366).
Claim 12. Fardad teaches a device, comprising: a first sense amplifier situated under the first memory array and a second sense amplifier situated under the second memory array (sense amp circuitry situation under a DRAM memory array, Fardad Fig 3-5, sense amp bank formed under an edge memory mat, He Fig 2); and a, the plurality of first conductive segments disposed between the first memory array and the first sense amplifier and between the first memory array and the second sense amplifier (sense amp beneath the memory array an electrically coupled to its digit line, Fardad Fig 1 and 3-5) and (configured to is functional language) but are silent with respect to plurality of first conductive segments that extend alternately in a first direction and a second direction (bit lines and complementary bit lines arrange in a zigzag pattern, Lee [0059] Fig 2); a first memory array and a second memory array that is spaced apart from the first memory array; electrically connect the first sense amplifier and the second sense amplifier to the first memory array.
Lee teaches plurality of first conductive segments that extend alternately in a first direction and a second direction (bit lines and complementary bit lines arrange in a zigzag pattern, Lee [0059] Fig 2). He teaches a first memory array and a second memory array that is spaced apart from the first memory array (multiple neighboring memory array mats, He Fig 2 col 7 lines 1-45); electrically connect the first sense amplifier and the second sense amplifier to the first memory array (different sense amp banks coupled to respective sets of bit lines associated with neighboring memory array mats, He Fig 2 col 7 lines 1-45) for the purpose of permitting bit line sense amps to be constructed as memory cell and bit line pitch decreases (Lee [0061] Fig 2) and efficiently using memory cells of the edge memory array matt by avoiding bit lines and corresponding memory cells from being unused, providing greater memory density (He Col 5 lines 40-48, Fig 2).
Since Fardad, Lee and He are from the same field of endeavor (bitline and sense amp circuit in semiconductor memory), the purpose disclosed by Lee and He would have been recognized in the pertinent art of Fardad.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the zigzag bit line routing taught by Lee in the memory circuit taught bv Fardad for the purpose of permitting bit line sense amps to be constructed as memory cell and bit line pitch decreases efficiently using memory cells of the edge memory array matt by avoiding bit lines and corresponding memory cells from being unused, providing greater memory density.
Claim 13. The device of claim 12, comprising: a plurality of second conductive segments that extend alternately in the first direction and the second direction (zigzag conductive routing, Lee [0059] Fig 2), the plurality of second conductive segments disposed between the second memory array and the first sense amplifier and between the second memory array and the second sense amplifier (sense amp circuitry associated with and situate beneath a memory array , Fardad Fig 3-5, He Fig 2) and (configured to is functional language) electrically connect the first sense amplifier and the second sense amplifier to the second memory array (first and second sense amp banks coupled to respective sets of bit lines of adjacent memory array mats, He Fig 2 Col 7 lines 1-45).
Claim 14. The device of claim 12, comprising a first word line driver situated under the first memory array (sub word line driver situated beneath the memory core, Fardad Fig 4-5) and a second word line driver situated under the second memory array (repeated sub word line driver architecture beneath memory core regions, Fardad Figs 4-5).
Claim 15. The device of claim 14, comprising a plurality of third conductive segments that extend alternately in the first direction and the second direction (zigzag conductive routing, Lee [0059] Fig 2), the plurality of third conductive segments disposed between the first memory array and the first word line driver (sub word line driver beneath the memory array with interconnect routing to the word line, Fardad Figs 5-8) and (configured to is functional language) electrically connect the first word line driver to the first memory array (sub word line driver 509 and word line 503, Fardad Fig 5), and a plurality of fourth conductive segments that extend alternately in the first direction and the second direction (zigzag conductive routing, Lee [0059] Fig 2), the plurality of fourth conductive segments disposed between the second memory array and the second word line driver (corresponding sub word line driver beneath a memory array, Fardad Fig 4-8) and (configured to is functional language) electrically connect the second word line driver to the second memory array (sub word line driver and associated word line connection Fardad Fig 5-8).
Claim 16. The device of claim 14, wherein the first memory array has an array footprint that has a middle portion and a footprint boundary, and the first word line driver is situated in the middle portion of the array footprint (sub word line driver circuitry disposed beneath the memory core, Fardad Figs 4-5) and the first sense amplifier is situated near the footprint boundary of the array footprint (sense amp bank position near an end of a memory array mat and between neighboring memory array mats, He Fig 2 Col 7 lines 1-15).
Claim 17. The device of claim 14, wherein the first memory array has an array footprint that has a middle portion and a footprint boundary, and the first sense amplifier is situated in the middle portion of the array footprint (sense amp bank 230 positioned between sections 210(1) and 210(2) of the edge memory array mat, He Fig 2 Col 7 Lines 1-15) and the first word line driver is situated near the footprint boundary of the array footprint (sub word line driver circuity positioned beneath the memory core relative to word line contact regions, Fardad Figs 3-5).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (Patent Application Publication 2023/0397410) in view of Yang (Patent Application Publication 2021/0104516).
Claim 18. Jain teaches a method of manufacturing a semiconductor device, the method comprising: forming front-end-of-line devices including a first sense amplifier, a first word line driver, a second sense amplifier, and a second word line driver on a substrate (front end peripheral circuitry for accessing multiple back end memory arrays, including sense and word line circuitry, Jain Fig 1-8); forming back-end-of-line memory arrays adjacent each other and electrically connected to the first back-end-of-line metal routing layers (multiple BEOL memory arrays accessed by underlying peripheral circuitry, Jain Figs 2-7); but is silent with respect to forming middle-end-of-line layers over the front-end-of-line devices; forming first back-end-of-line metal routing layers over the middle-end-of-line layers; and forming second back-end-of-line metal routing layers over the back-end-of-line memory arrays.
Yang teaches forming middle-end-of-line layers over the front-end-of-line devices (interconnect layer formed above peripheral device circuitry and including MOEL interconnects, Yang Fig 5C operation 1104 of Fig 11); forming first back-end-of-line metal routing layers over the middle-end-of-line layers (interconnect layer 512 includes MEOL and BEOL interconnects in multiple IDL layers, Yang Fig 5C, operation 1104 of Fig 11); and forming second back-end-of-line metal routing layers over the back-end-of-line memory arrays (interconnect layer 620 formed above memory stack 604 and array of memory strings 610 and including BEOL interconnects, Yang Fig 6B operation 112 Fig 11) for the purpose of making electrical connections with the device layer and array (interconnect layer 512 makes electrical connections with 510 and interconnect layer 620 with strings 610, Yang Fig 5C, 6B and 11).
Since Jain and Yang are both from the same field of endeavor (vertically semiconductor memory connected and interconnecting structures), the purpose disclosed by Yang would have been recognized in the pertinent art of Jain.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the MEOL and BEOL interconnect structure taught by Yang in the memory circuit taught by Jain for the purposes of making electrical connections with the device layer and memory arrays.
Claim 19. The method of claim 18, wherein forming back-end-of-line memory arrays includes: forming a first memory array above the first sense amplifier and the first word line driver (BEOL memory array positioned above footprint region containing sense amplifier and word line driver circuit, Jain Fig 5-7); and forming a second memory array above the second sense amplifier and the second word line driver (additional BEOL memory array positioned above another footprint region containing sense amplifier and word line driver circuitry, Jason Fig 5-7).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jain (Patent Application Publication 2023/0397410) in view of Yang (Patent Application Publication 2021/0104516) further in view of He (U.S. Patent Application 11024366).
Claim 20. Jain and Yang teach the method of claim 19 but are silent with respect to forming conductive segments configured to connect each of the first and second sense amplifiers to each of the first and second memory arrays.
He discloses wherein forming middle-end-of-line layers and forming first back-end-of-line metal routing layers includes forming conductive segments (configured to is functional language) connect the first sense amplifier to each of the first memory array and the second memory array and to connect the second sense amplifier to each of the first memory array and the second memory array (sense amplifier banks coupled to bitline associated with neighboring mats, He Fig 2 Col 7 lines 1-45), for the purpose of efficiently using cell by avoiding unused bit line and corresponding memory cells allowing greater memory density (He Col 5 lines 40-48 Fig 2).
Since Jain Yang and He are from the same field of endeavor (sensing circuitry in semiconductor memory), the purpose disclosed by He would have been recognized in the pertinent art of Jain and Yang.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the neighboring memory array sense amp connections taught by He in the BEOL memory circuit taught by Jain for the purposes of efficiently using cell by avoiding unused bit line and corresponding memory cells allowing greater memory density.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827
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