DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-2 and 6 are amended. Claims 1-6 are present for examination.
Claim Rejections - 35 USC § 102
Applicant’s arguments, see pages 4-7, filed May 14, 2026, with respect to the rejection(s) of claim 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chuang in view of Lu (US 2021/0384195 A1).
Response to Arguments
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define the relative overlapping structure of the above lying upper semiconductor structure and the under lying lower semiconductor structure in a vertical direction perpendicular to the substrate (e.g. (i) wherein the first upper semiconductor structure is disposed over and entirely overlaps the first lower semiconductor structure in a vertical direction, (ii) wherein the second upper semiconductor structure is disposed over and entirely overlaps the second lower semiconductor structure in a vertical direction). The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang (US 2015/0129969 A1) in view of Lu (US 2021/0384195 A1).
Claim 1, Chuang discloses the semiconductor device structure (Fig. 6, 7, First Annotated Fig. 9), comprising:
a first lower semiconductor structure (720 as seen in Fig. 7 is doped polysilicon, 620 in Fig. 6 is equivalent to 720 in Fig. 7, para [0021]) disposed on top of a semiconductor substrate (substrate 200, para [0022]), wherein the first lower semiconductor structure 720 has a first sidewall (left sidewall 720 as shown in First Annotated Fig. 9) and a second sidewall (right slanted sidewall of 720 as shown in First Annotated Fig. 9) opposite to the first sidewall (both sidewalls are oriented opposite to each other across 720);
a first upper semiconductor structure (920 over the region of 740 and includes polysilicon, para [0011]) covering a top surface (top surface of 720) and the first sidewall (left sidewall of 720) of the first lower semiconductor structure 720, wherein the first lower semiconductor structure 720 and the first upper semiconductor structure 920 comprise different materials (720 is doped polysilicon while 920 includes polysilicon);
a first oxide portion (910 includes silicon oxide, para [0024]) disposed over the semiconductor substrate 200 and extending along the second sidewall (right sidewall of 720 as also denoted by 750 as the second sidewall in Fig. 9) of the first lower semiconductor structure 720 (910 is on the right-hand side of 720);
a dielectric layer 930 disposed over the first oxide portion 910, wherein the first oxide portion 910 separates the dielectric layer 930 from the semiconductor substrate 200 (dielectric layer 930 disposed over the first oxide portion 910, wherein the first oxide portion 910 separates the dielectric layer 930 from the semiconductor substrate 200);
a second lower semiconductor structure (Fig. 8 illustrates 620 is doped polysilicon within gate stack 820, para [0021, 0023]) disposed on top of the semiconductor substrate 200, wherein the second lower semiconductor structure 820 has a third sidewall (right sidewall of 820) facing the second sidewall (right sidewall of 720) of the first lower semiconductor structure 820 and a fourth sidewall (left sidewall of 820) opposite to the third sidewall (third sidewall is facing the second sidewall and fourth sidewall is opposite to the third sidewall);
a second upper semiconductor structure (920 include polysilicon within the region of 820, para [0024]) covering a top surface (Fig. 8 illustrates top surface of layer 620 within the region of 820) and the third sidewall (right sidewall of 820) of the second lower semiconductor structure 820 (820 is doped polysilicon while 920 includes polysilicon);
a second oxide portion (910 within the region of 820, hereinafter “2nd”) disposed over the semiconductor substrate 200 and extending along the fourth sidewall (left sidewall of 820) of the second lower semiconductor structure 820, wherein the second oxide portion is covered by the dielectric layer 930 (2nd is covered by the dielectric layer 930);
wherein the first oxide portion 910 is in direct contact with a sidewall of the second upper semiconductor structure 920 (first oxide portion 910 is in direct contact with a sidewall of the second upper semiconductor structure 920);
wherein a material of the first oxide portion 910 is the same as a material of the second oxide portion 2nd (910 is silicon oxide and is the same material as the first and second oxide portions).
Chang does not explicitly disclose a first lower semiconductor structure disposed on a top surface of a semiconductor substrate, a second lower semiconductor structure disposed on the top surface of the semiconductor substrate, wherein the first oxide portion is in direct contact with a sidewall of the second upper semiconductor structure; and is in direct contact with the top surface of the semiconductor substrate; wherein the second oxide portion is in direct contact with the top surface of the semiconductor substrate.
However, Lu discloses a first lower semiconductor structure (Lu, bit line (UGBL) is a first lower semiconductor structure, hereinafter, first lower semiconductor structure UGBL_1, [0225], Fig. 30; Chang, 720 as seen in Fig. 7 is doped polysilicon, 620 in Fig. 6 is equivalent to 720 in Fig. 7, para [0021]) disposed on a top surface of a semiconductor substrate (Lu, first lower semiconductor structure UGBL_1 is disposed on a top surface of semiconductor substrate 202 further including STI, hereinafter, semiconductor substrate 202, [0192], Fig. 30; Chang, substrate 200, para [0022]), wherein the first lower semiconductor structure has a first sidewall (Lu, first lower semiconductor structure UGBL_1 has a first sidewall on the left-hand side of the first lower semiconductor structure UGBL_1, hereinafter first sidewall UGBL_1L, [0192], Fig. 30; Chang, left sidewall 720 as shown in First Annotated Fig. 9) and a second sidewall (Lu, first lower semiconductor structure UGBL_1 has a second sidewall on the right-hand side of the first lower semiconductor structure UGBL_1, hereinafter second sidewall UGBL_1R, [0192], Fig. 30; Chang, right slanted sidewall of 720 as shown in First Annotated Fig. 9) opposite to the first sidewall (Lu, first sidewall UGBL_1L is opposite to the second sidewall UGBL_1R, [0192], Fig. 30; Chang, both sidewalls are oriented opposite to each other across 720);
a first upper semiconductor structure (Lu, CVD-STI-Oxide2 1002 is a first upper semiconductor structure, hereinafter, first upper semiconductor structure 1002_1, [0202], Figs. 10 and 30; Chang, 920 over the region of 740 and includes polysilicon, para [0011]) covering a top surface (Lu, first upper semiconductor structure 1002_1 is covering a top surface of the first lower semiconductor structure UGBL_1, hereinafter, top surface UGBL_1T, [0202], Figs. 10 and 30; Chang, top surface of 720) and the first sidewall (Chang, left sidewall of 720; Lu, first upper semiconductor structure 1002_1 covers a top surface of the first sidewall UGBL_1L, [0202], Figs. 10 and 30) of the first lower semiconductor structure (Lu, first upper semiconductor structure 1002_1 covers a top surface of the first sidewall UGBL_1L, [0202], Figs. 10 and 30; Chang, top surface of 720), wherein the first lower semiconductor structure and the first upper semiconductor structure comprise different materials (Lu, first lower semiconductor structure UGBL_1 (i.e. metal layer) and the first upper semiconductor structure 1002_1 (i.e. oxide) comprise different materials; Chang, 720 is doped polysilicon while 920 includes polysilicon);
a first oxide portion (Lu, oxide-1 layer 504 is a first oxide portion, hereinafter, first oxide portion 504_1, [0197], Fig. 30; Chang, 910 includes silicon oxide, para [0024]) disposed over the semiconductor substrate and extending along the second sidewall (Lu, first oxide portion 504_1 is disposed over the semiconductor substrate 202 and extending along the second sidewall UGBL_1R of the first lower semiconductor structure UGBL_1, [0197], Fig. 30; Chang, right sidewall of 720 as also denoted by 750 as the second sidewall in Fig. 9) of the first lower semiconductor structure (Lu, first oxide portion 504_1 is disposed over the semiconductor substrate 202 and extending along the second sidewall UGBL_1R of the first lower semiconductor structure UGBL_1, [0197], Fig. 30; Chang, 910 is on the right-hand side of 720);
a dielectric layer disposed over the first oxide portion, wherein the first oxide portion separates the dielectric layer from the semiconductor substrate (Lu, nitride-5 layer 1802 is a dielectric layer, hereinafter, dielectric layer 1802 is disposed over the first oxide portion 504_1, wherein the first oxide portion 504_1 separates the dielectric layer 1802 from the semiconductor substrate 202, Fig. 30; Chang, dielectric layer 930 disposed over the first oxide portion 910, wherein the first oxide portion 910 separates the dielectric layer 930 from the semiconductor substrate 200);
a second lower semiconductor structure (Lu, bit line (UGBL) to the right-hand side of the first lower semiconductor structure UGBL_1 is a second lower semiconductor structure, hereinafter, second lower semiconductor structure UGBL_2, [0225], Fig. 30; Chang, Fig. 8 illustrates 620 is doped polysilicon within gate stack 820, para [0021, 0023]) disposed on the top surface of the semiconductor substrate, wherein the second lower semiconductor structure has a third sidewall (Lu, second lower semiconductor structure UGBL_2 is disposed on the top surface of the semiconductor substrate 202, wherein the second lower semiconductor structure UGBL_2 has a third sidewall UGBL_2L, [0225], Fig. 30; Chang, right sidewall of 820) facing the second sidewall (Lu, second lower semiconductor structure UGBL_2 has a third sidewall UGBL_2L facing the second sidewall UGBL_1R, [0225], Fig. 30; Chang, right sidewall of 720) of the first lower semiconductor structure and a fourth sidewall (Lu, second lower semiconductor structure UGBL_2 has a third sidewall UGBL_2L facing the second sidewall UGBL_1R of the first lower semiconductor structure UGBL1 and a fourth sidewall UGBL_2R, [0225], Fig. 30; Chang, left sidewall of 820) opposite to the third sidewall (Lu, second lower semiconductor structure UGBL_2 has a fourth sidewall UGBL_2R opposite to the third sidewall UGBL_2L, [0225], Fig. 30; Chang, third sidewall is facing the second sidewall and fourth sidewall is opposite to the third sidewall);
a second upper semiconductor structure (Lu, CVD-STI-Oxide2 1002 is a second upper semiconductor structure to the right-hand side of the first upper semiconductor structure 1002_1, hereinafter, second upper semiconductor structure 1002_2, [0202], Figs. 10 and 30; Chang, 920 include polysilicon within the region of 820, para [0024]) covering a top surface (Lu, second upper semiconductor structure 1002_2, [0202], Figs. 10 and 30; Chang, Fig. 8 illustrates top surface of layer 620 within the region of 820) and the third sidewall (Lu, second upper semiconductor structure 1002_2, [0202], Figs. 10 and 30; Chang, right sidewall of 820) of the second lower semiconductor structure (Lu, second upper semiconductor structure 1002_2 covers a top surface of the third sidewall UGBL_2L of the second lower semiconductor structure UGBL_2, [0202], Figs. 10 and 30; Chang, 820 is doped polysilicon while 920 includes polysilicon);
a second oxide portion (Lu, oxide-1 layer 504 is a second oxide portion to the right-hand side of the first oxide portion 504_1, hereinafter, second oxide portion 504_2, [0197], Fig. 30; Chang, 910 within the region of 820, hereinafter “2nd”) disposed over the semiconductor substrate and extending along the fourth sidewall (Lu, second oxide portion 504_2 is disposed over the semiconductor substrate 202 and extending along the fourth sidewall UGBL_2R, [0197], Fig. 30; Chang, left sidewall of 820) of the second lower semiconductor structure, wherein the second oxide portion is covered by the dielectric layer (Lu, second oxide portion 504_2 is covered by the dielectric layer 1802, [0197], Fig. 30; Chang, 2nd is covered by the dielectric layer 930);
wherein the first oxide portion is in direct contact with a sidewall of the second upper semiconductor structure (Lu, first oxide portion 504_1 is in contact with a sidewall of the second upper semiconductor structure 1002_2, [0197], Fig. 30; Chang, first oxide portion 910 is in direct contact with a sidewall of the second upper semiconductor structure 920); and is in direct contact with the top surface of the semiconductor substrate (Lu, first oxide portion 504_1 is in direct contact with the top surface of the semiconductor substrate 202, [0197], Fig. 30; Chang, first oxide portion 910 is in direct contact with a sidewall of the second upper semiconductor structure 920);
wherein the second oxide portion is in direct contact with the top surface of the semiconductor substrate (Lu, second oxide portion 504_2 is in direct contact with the top surface of the semiconductor substrate 202, [0197], Fig. 30; Chang, first oxide portion 910 is in direct contact with a sidewall of the second upper semiconductor structure 920);
wherein a material of the first oxide portion is the same as a material of the second oxide portion (Lu, material of the first oxide portion 504_1 is the same as a material of the second oxide portion 504_2, [0197], Fig. 30; Chang, 910 is silicon oxide and is the same material as the first and second oxide portions).
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First Annotated Fig. 9 (Chuang) – Illustrates the first and second sidewalls, first lower semiconductor structure 720, and first upper semiconductor structure 920
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Second Annotated Fig. 9 (Chuang) – Illustrates the third and fourth sidewalls, second lower semiconductor structure 820, and second upper semiconductor structure 920
Claim 2, Chuang/Lu discloses the semiconductor device structure (Chuang, Fig. 9; Lu, Fig. 30) of claim 1.
Chuang/Lu discloses wherein the first upper semiconductor structure is in direct contact with the top surface and the first sidewall of the first lower semiconductor structure (Chuang; first upper semiconductor structure 920 is in direct contact with the top surface and the first sidewall of the first lower semiconductor structure 720; Lu, Fig. 30), and
wherein the first oxide portion is in direct contact with the second sidewall of the first lower semiconductor structure (Chuang; first oxide portion 910 is in direct contact with the second sidewall of the first lower semiconductor structure 720; Lu, Fig. 30);
wherein the second oxide portion is in direct contact with the fourth sidewall of the second lower semiconductor structure (Lu, second oxide portion 504_2 is in direct contact with the fourth sidewall UGBL_2R of the second lower semiconductor structure UGBL_2, [0197], Fig. 30; Chang, first oxide portion 910 and second upper semiconductor structure 920).
Claim 3, Chuang/Lu discloses the semiconductor device structure (Chuang, Fig. 9; Lu, Fig. 30) of claim 1.
Chuang/Lu discloses wherein the first lower semiconductor structure and the dielectric layer are separated by the first upper semiconductor structure and the first oxide portion (Chuang, first lower semiconductor structure 720 and the dielectric layer 930 are separated by the first upper semiconductor structure 920 and the first oxide portion 910; Lu, Fig. 30).
Claim 5, Chuang/Lu discloses the semiconductor device structure (Chuang, Fig. 9; Lu, Fig. 30) of claim 1.
Chuang/Lu discloses wherein a bottom surface of the first upper semiconductor structure is higher than a bottom surface of the first lower semiconductor structure (Chuang, bottom surface of 920 is higher than the bottom surface of 720; Lu, Fig. 30).
Claim 6, Chuang/Lu discloses the semiconductor device structure (Chuang, Fig. 9; Lu, Fig. 30) of claim 1.
Chuang/Lu discloses wherein the first oxide portion 910 is in direct contact with the first upper semiconductor structure 920 (Chuang, 910 is in direct contact with 920; Lu, Fig. 30), wherein the first lower semiconductor structure and the second lower semiconductor structure are in direct contact with the top surface of the semiconductor substrate (Lu, first lower semiconductor structure UGBL_1 is in electrical contact and includes the first tungsten plug (i.e. left-hand side of first lower semiconductor structure UGBL_1) and second lower semiconductor structure UGBL_2 is in electrical contact and includes the second tungsten plug (i.e. right-hand side of first lower semiconductor structure UGBL_1 and left-hand side of second lower semiconductor structure UGBL_2) and are disposed in direct contact with the top surface of the semiconductor substrate 202, [0225], Fig. 30; Chang, Fig. 8 illustrates 620 is doped polysilicon within gate stack 820, para [0021, 0023]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang in view of Lu, further in view of Lee (US 2006/0194418 A1).
Claim 4, Chuang/Lu discloses the semiconductor device structure (Chuang, Fig. 9; Lu, Fig. 30) of claim 1.
Chuang/Lu discloses wherein the first lower semiconductor structure comprises doped polysilicon (Chuang, 720 as seen in Fig. 7 is doped polysilicon, 620 in Fig. 6 is equivalent to 720 in Fig. 7, para [0021]; Lu, Fig. 30).
Chuang/Lu does not explicitly disclose the first upper semiconductor structure comprises germanium (Ge).
However, Lee discloses in para [0040] that germanium can be used as a local interconnection between the Ge device and Si bottom device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee, including the specific material of the interconnect, germanium, to the teachings of Chuang/Lu.
The motivation to do so is that the combination yields the predictable results of allowing for the selection of a known material based on its suitability for the intended use as an interconnect. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Itou (US 2012/0256266 A1) discloses a semiconductor device (Fig. 7B) with a polysilicon gate electrode and oxide spacers.
Lee (US 2006/0194418 A1) discloses in para [0040] that germanium can be used as a local interconnection between the Ge device and Si bottom device.
Chuang (US 2015/0129969 A1) discloses the semiconductor device structure (Fig. 6, 7, First Annotated Fig. 9), comprising:
a first lower semiconductor structure 740/910 (720 as seen in Fig. 7 is doped polysilicon, 620 in Fig. 6 is equivalent to 720 in Fig. 7, para [0021]), 910 is included in the structure 740) disposed over a semiconductor substrate (substrate 200, para [0022]), wherein the first lower semiconductor structure 740/910 has a first sidewall (left sidewall of 740/910) and a second sidewall (right slanted sidewall of 740/910 as also denoted by 750 as the second sidewall in Fig. 9) opposite to the first sidewall (both sidewalls are oriented opposite to each other across 740/910);
a first upper semiconductor structure (920 over the region of 740 and includes polysilicon, para [0011]) covering a top surface (top surface of 740/910) and the first sidewall (left sidewall of 740/910) of the first lower semiconductor structure 740/910, wherein the first lower semiconductor structure 740/910 and the first upper semiconductor structure 920 comprise different materials (720 is doped polysilicon while 920 includes polysilicon); and
a first portion (mask layer 930, para [0024]) disposed over the semiconductor substrate 200 and extending along the second sidewall (930 is disposed over 200 and extending along the right sidewall of 740/910, see Alt. First Annotated Fig. 9) of the first lower semiconductor structure 740, wherein the first oxide portion has an L-shape (930 has an L-shape in trench 750 on the right-hand side of 740/910).
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Alt. First Annotated Fig. 9 – Illustrates the first lower semiconductor structure 740/910 and first upper semiconductor structure 920
Yelehanka (US 2004/0155269 A1) discloses a semiconductor device structure (Figs. 1 and 5), comprising:
a first lower semiconductor structure (semiconductor gate 108, para [0025]) disposed over a semiconductor substrate 102, wherein the first lower semiconductor structure 108 has a first sidewall (right hand side of 108) and a second sidewall (left hand side of 108) opposite to the first sidewall (both sidewalls are oriented opposite to each other);
a first upper structure 150 covering a top surface (top surface of 108) and the first sidewall (right hand side of 108) of the first lower semiconductor structure 108, wherein the first lower semiconductor structure 108 and the first upper semiconductor structure 150 comprise different materials (108 is a gate while 150 is an interconnect made of a conductive material such as W/Ta/Ti, para [0036]); and
a first oxide portion (134 is an oxide and equivalent to 121 in Fig. 1, para [0034]) disposed over the semiconductor substrate 102 and extending along the second sidewall (left hand side of 108) of the first lower semiconductor structure 108, wherein the first oxide portion has an L-shape (134 has an L-shape).
Yelehanka does not explicitly disclose a first upper semiconductor structure.
However, Lee discloses in para [0040] that germanium can be used as a local interconnection between the Ge device and Si bottom device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee, including the specific material of the interconnect, germanium, to the teachings of Yelehanka.
The motivation to do so is that the combination yields the predictable results of allowing for the selection of a known material based on its suitability for the intended use as an interconnect. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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