DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 7/1/2026. Claims 1-20 are pending and have been examined. Claims 1-10, 15 and 20 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claim 15 recites the following contingent limitations: “…in response to a call of an application programming interface (API), canceling one or more scheduled instructions identified by one or more software programs from being performed.”.
The contingent limitation uses the language “in response to” and is contingent because it precedes steps that are only required to be performed in response to (i.e. if) a condition being met. For example, the steps of “canceling one or more scheduled instructions” are only required to be performed in response to (e.g. “if”) a call of an API. However, if an API is not called the steps of “cancelling scheduled instructions” are not required to occur based on the broadest reasonable interpretation given to contingent limitations in method claims (See MPEP 2111.04(II) See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016)).
The examiner suggests amending the claim to remove the contingent limitations and to positively recite each step of the method claim. For example, amending the claim to state “…receiving a call [[of]] to an application programming interface (API)…”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 8, 15 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gittelman, PGPUB No. 2013/0055266 (cited on 892 filed on 4/1/2026).
In regard to claim 1, Gittelman discloses One or more processors ([0023-0024 and 0082-0084: wherein a computing environment comprising one or more CPUs is disclosed) comprising: circuitry to, in response to a call of an application programming interface (API): cancel one or more scheduled instructions identified by one or more software programs from being performed. ([0012-0013, 0025, 0031, 0039, 0043, 0059 and 0063]: wherein in response to an API call to a cancel function one or more scheduled (e.g. arranged or planned) commands of a command block identified by software programs running tasks are canceled from being performed (also see [0047 and 0083-0088] for further discussion of software programs and Figs. 1-3 and 6))
Claim 8 is similarly rejected on the same basis as claim 1 above as claim 8 is the system corresponding to the processor of claim 1 above.
Claim 15 is similarly rejected on the same basis as claim 1 above as claim 15 is the method corresponding to the processor of claim 1 above.
In regard to claim 4, Gittelman discloses The one or more processors processor of claim 1 (see rejection of claim 1 above) wherein the circuitry to identify the one or more scheduled instructions based, at least in part, on one or more data structures. ([0059]: wherein the one or more scheduled commands are identified using a list data structure)
In regard to claim 20, Gittelman discloses The method of claim 15 (see rejection of claim 15 above) wherein the one or more scheduled instructions are associated with the one or more software programs from one or more users. ([0011, 0025 and 0027]: wherein one or more scheduled commands are associated with one or more software programs from programmers/users)
Claim(s) 1-2, 4-5, 7-9, 11,13, 15, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wilt, USPAT No. 8,539,516.
In regard to claim 1, Wilt discloses One or more processors (See Fig. 1, element 110) comprising: circuitry, to in response to a call of an application programming interface (API) (Column 3, lines 1-67: wherein host includes a CPU to perform a CUDA API in response to a call) cancel one or more scheduled instructions identified by one or more software programs from being performed. (Column 7, lines 20 to 67 to Column 8, lines 1-41 and Fig. 5: wherein CUDA API is performed to cancel (e.g. by suspending execution for a period of time the planned execution of the subsequent instructions is cancelled (stopped) from occurring during a period of time until a semaphore release is performed) one or more scheduled instructions identified, by one or more application programs which comprise said instructions, from being executed at a particular point in time (See Column 3, lines 38-50, Column 5, lines 61-64 and Column 11, lines 10-11 for details on application programs))
Claim 8 is similarly rejected on the same basis as claim 1 above as claim 8 is the system corresponding to the processor of claim 1 above.
Claim 15 is similarly rejected on the same basis as claim 1 above as claim 15 is the method corresponding to the processor of claim 1 above.
In regard to claim 2, Wilt discloses The one or more processors of claim 1 (see claim 1 above) wherein the one or more scheduled instructions are stored in one or more push buffers. (See Fig. 5, push buffers (elements 510 and 520) which store one or more scheduled instructions)
In regard to claim 4, Wilt discloses The one or more processors of claim 1 (see claim 1 above) wherein the circuitry is to identify the one or more scheduled instructions based, at least in part, on one or more data structures. (Column 3, lines 38-67: wherein host identifies instructions based at least in part on one or more software stacks (data structures) including program instructions which are scheduled for execution on element 130 (see Fig. 1 and 5))
In regard to claim 5, Wilt discloses The one or more processors of claim 1 (see rejection of claim 1 above) wherein the circuitry is to identify whether the one or more scheduled instructions have been obtained by one or more components of one or more processing units. (Column 8, lines 1-46: wherein it is determined whether one or more components of computing device (element 134) have obtained one or more scheduled instructions of a push buffer or not, depending on if instructions have been suspended and must wait until preceding commands and a semaphore release instruction is executed (e.g., have not been obtained if semaphore release has not executed) (See Fig. 5))
In regard to claim 7, Wilt discloses The one or more processors of claim 1 (see claim 1 above) wherein the one or more scheduled instructions are to be performed by one or more graphics processing units (GPUs). (Column 4, lines 7-16, Column 7, lines 53-64 and See Fig. 5: wherein computing device (element 134) includes one or more streaming multiprocessors that execute graphics commands)
In regard to claim 9, Wilt discloses The system of claim 8 (see rejection of claim 8 above) wherein the one or more processors are to, as a result of identifying that the one or more scheduled instructions have not been obtained by one or more components of a processing unit, cancel the one or more scheduled instructions from being performed by the processing unit. (Column 8, lines 1-46: wherein it is determined that one or more components of computing device (element 134) have not obtained one more scheduled instruction of a push buffer and then the one or more instructions are suspended (stopped and thus cancelled) from execution until preceding commands and a semaphore release instruction are executed (See Fig. 5))
In regard to claim 11, Wilt discloses The system of claim 8 (see rejection of claim 8 above) wherein one or more input parameters to the API comprise an indication of a data structure indicating the one or more scheduled instructions. (Column 8, lines 10-46, Column 10, lines 39-67 to Column 11, lines 1-35: wherein map and unmap parameters comprise an indication, which configures insertion of semaphore instructions into push buffer, that indicates a data structure (push buffer) storing the scheduled instructions)
In regard to claim 13, Wilt discloses The system of claim 8 (see rejection of claim 8 above) wherein the one or more processors are to generate one or more semaphore release methods to prevent the one or more scheduled instructions from being performed. (Column 7, lines 33-67 to Column 8, lines 1-46: wherein a method of using a semaphore release command is used to prevent one or more scheduled instructions from being executed until the semaphore release command is executed prior)
In regard to claim 18, Wilt discloses The method of claim 15 (see rejection of claim 15 above) further comprising identifying one or more channels associated with the one or more scheduled instructions. (Column 7, lines 57-64 to Column 8, lines 1-46 and See Fig. 5)
In regard to claim 20, Wilt discloses The method of claim 15 (see rejection of claim 15 above) wherein the one or more scheduled instructions are associated with the one or more software programs from one or more users. (Column 3, lines 39-56 and Fig. 1: wherein the scheduled instructions are associated with one or more programs from the application developer (for further clarity see Column 5, lines 61-64 and Column 11, lines 10-11 for details on application developer and program))
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 10, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilt, and further in view of Yamasaki, USPAT No. 6,370,638.
In regard to claim 3, Wilt discloses The one or more processors of claim 1 (see rejection of claim 1 above).
Wilt does not disclose wherein the circuitry is to generate one or more no-op instructions to cancel the one or more scheduled instructions from being performed.
Yamasaki discloses wherein the circuitry is to generate one or more no-op instructions to cancel the one or more instructions from being performed. (Column 8, lines 55-65 and Column 15, lines 10-18: wherein no-op operations are generated and inserted to stop the instructions from being processed (See Figs. 6-10 for details on NOP generation circuits))
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the processor of Wilt, which stops instruction execution to, insert a number of no-ops to stop execution as taught in Yamasaki. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using no-operation instructions to stop execution of latter instructions in a processor as taught in Yamasaki) for another (stopping execution of latter instructions in a processor using semaphore instructions as taught in Wilt) to yield predictable results (stopping execution of instructions by inserting no-operation instructions before said instructions) (MPEP 2143, Example B)
In regard to claim 10, Wilt discloses The system of claim 8 (see rejection of claim 8 above). wherein the one or more processors are to store instructions in one or more push buffers (See Fig. 5, push buffers (elements 510 and 520) which store one or more instructions)
Wilt does not disclose wherein the one or more processors are to store one or more no-op instructions to cancel the one or more scheduled instructions from being performed.
Yamasaki discloses wherein the one or more processors are to insert one or more no-op instructions to cancel the one or more scheduled instructions from being performed. (Column 8, lines 55-65 and Column 15, lines 10-18: wherein no-op operations are inserted to stop the instructions from being processed (See Figs. 6-10 for details on NOP generation circuits))
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the processor of Wilt, which stops instruction execution of scheduled instructions in one or more push buffers, to insert a number of no-ops to stop execution as taught in Yamasaki. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using no-operation instructions to stop execution of latter instructions in a processor as taught in Yamasaki) for another (stopping execution of instructions in a push buffer using semaphore instructions in a processor as taught in Wilt) to yield predictable results (stopping execution of instructions in a one or more push buffers by inserting no-operation instructions before said instructions in one or more push buffers) (MPEP 2143, Example B)
Claim 16 is similarly rejected on the same basis as claims 3 and 10 above as claim 16 is the method corresponding to the processor of claim 3 and the system of claim 10 above.
Claim(s) 6, 12, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilt, and further in view of Vaz, PGPUB No. 2023/0185635.
In regard to claim 6, Wilt discloses The one or more processors of claim 1 (see rejection of claim 1 above) wherein the circuitry is to obtain one or more semaphore commands based, at least in part, on the one or more scheduled instructions. (Column 7, lines 53-67 to Column 8, lines 1-45)
Wilt does not disclose wherein the circuitry is to obtain one or more semaphore values. Wilt discloses using semaphore commands and a semaphore buffer (See Fig. 4 and Column 5, lines 39-52) but does not explicitly disclose the commands or buffer using semaphore values.
Vaz discloses wherein the circuitry is to obtain one or more semaphore values. ([0093 and 0104]: wherein semaphore commands uses semaphore values)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the semaphore commands of Wilt to use semaphore values as the semaphore commands as taught in Vaz. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using semaphore values in semaphore commands as taught in Vaz) for another (generic semaphore commands as taught in Wilt) to yield predictable results (semaphore commands using semaphore values to synchronize processing) (MPEP 2143, Example B). Furthermore, synchronizing can reduce wasting computing resources (Vaz [0049]).
In regard to claim 12, Wilt discloses The system of claim 8 (see rejection of claim 8 above) wherein the one or more scheduled instructions (See Fig. 5)
Wilt does not disclose one or more instructions are associated with one or more kernels.
Vaz discloses one or more instructions are associated with one or more kernels. ([0088, 0099, 0277, 0307]: wherein one or more instructions of a function are associated with a kernel)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the instructions of Wilt to be associated with a kernel as the instructions taught in Vaz. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (instructions associated with a kernel as taught in Vaz) for another (generic instructions as taught in Wilt) to yield predictable results (scheduling instructions associated with a kernel) (MPEP 2143, Example B).
In regard to claim 17, Wilt discloses The method of claim 15 (see rejection of claim 15 above) further comprising using one or more semaphore to identify whether to prevent the one or more scheduled instructions (Column 7, lines 53-67 to Column 8, lines 1-45)
Wilt does not disclose one or more semaphore values to identify whether to prevent the one or more scheduled instructions. Wilt discloses using semaphore commands and a semaphore buffer (See Fig. 4 and Column 5, lines 39-52) but does not explicitly disclose the commands or buffer using semaphore values.
Vaz discloses one or more semaphore values to identify whether to prevent the one or more operations. ([0093 and 0104]: wherein semaphore values identify whether one or more operations are to wait (prevented))
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the semaphore commands of Wilt to use semaphore values as the semaphore commands as taught in Vaz. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using semaphore values in semaphore commands as taught in Vaz) for another (generic semaphore commands as taught in Wilt) to yield predictable results (semaphore commands using semaphore values to synchronize processing) (MPEP 2143, Example B). Furthermore, synchronizing can reduce wasting computing resources (Vaz [0049]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilt, and further in view of Hakke Patil, PGPUB No. 2023/0087457.
In regard to claim 14, Wilt discloses The system of claim 8 (see rejection of claim 8 above).
Wilt does not disclose wherein a return of the API includes one or more status indications.
Hakke Patil discloses wherein a return of an API includes one or more status indications. ([0128, 0131 and 0449])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the API of Wilt to return a status indicator as the API of Hakke Patil. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (returning a status indicator from an API as taught in Hakke Patil) for another (not returning a status indicator from an API as taught in Wilt) to yield predictable results (returning a status indicator from an API) (MPEP 2143, Example B). Additionally, allowing an API to return status indicators would allow effective communication of instruction completion or if an error occurred in a system, thus communicating whether or not error correction would be required in the system.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilt, and further in view of Ashwathnarayan, PGPUB No. 2020/0364088.
In regard to claim 19, Wilt discloses The method of claim 15 (see rejection of claim 15 above).
Wilt does not disclose wherein one or more input parameters to the API comprise an identifier associated with the one or more scheduled instructions.
Ashwathnarayan discloses wherein one or more input parameters to the API comprise an identifier associated with the one or more instructions. ([0079-0080, 0096-0097, 0101-0102]: wherein one or more input parameters to the API comprise identifier (key) of an attribute associated with instructions to execute on heterogeneous cores (see abstract and Fig. 7))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the API of Wilt to use input parameters as the API of Ashwathnarayan. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using input parameters comprising an identifier as taught in Ashwathnarayan) for another (generic API as taught in Wilt) to yield predictable results (using an API with one or more input parameters comprising an identifier) (MPEP 2143, Example B). Additionally, using API for synchronization that uses attribute parameters can avoid dynamic memory allocations and reduces memory usage. (Ashwathnarayan [0072])
Response to Arguments
Applicants’ arguments filed on 7/1/2026 have been fully considered but they are not persuasive. Therefore, the previous 35 USC 102 rejections in view of Wilt have been maintained. Further, in light of compact prosecution the examiner has provided an additional 35 USC 102 rejection in view of Gittelman, PGPUB No. 2013/0055266 which also discloses the claim limitations of independent claims 1, 8 and 15.
Claims 2-7, 9-14 and 16-20 are argued at least based upon dependency and thus remain rejected at least based upon their dependencies.
Applicant argues the 102 rejections of similar claims 1, 8 and 15, on page 6 of the remarks, in the substance that:
“Without acquiescing to the rejection, claim 1 is amended to further expedite prosecution. In view of the Examiner's indication that the amendment overcomes the current rejection, Applicant respectfully submits that the rejection is moot. Accordingly, Applicant respectfully submits that claim 1 is allowable under 35 U.S.C. § 102 over Wilt.”
Upon further consideration of the amendment the examiner believes the prior art reference Wilt discloses the amended claim language under broad interpretation. For example, Wilt discloses in Fig. 5 that an API inserts a semaphore acquire command which suspends execution of subsequent commands until other pending commands and a semaphore release command are executed. Thus, Wilt discloses cancelling (e.g. stopping) execution of one or more scheduled subsequent instructions of a push buffer until a semaphore release command is executed. Said another way Wilt discloses cancelling scheduled instructions from being performed for a particular period (e.g. until a semaphore release is performed).
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Apodaca, PGPUB No. 2016/0364829 for teaching an API barrier call which terminates any patch and/or submit transactions in a GPU patch command buffer
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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