DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 9, and 16 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, and 14, respectively, of U.S. Patent No. 12230350 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed language is a more succinct version of the patented language and the scope of the claims are not patentable different.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dono, US 20030164510 A1.
As to claim 2, Dono discloses a method of operating a volatile memory device (see Fig 4) comprising a repair circuit (see Fig 4 Refs 110A and 110B), the method comprising:
receiving, at the volatile memory device, a control signal (see Fig 4 Reds In and In’) from a memory controller (see Fig 4 Refs 12, 16, 17, 18, and 21), the control signal to indicate a repair mode of operation (see Fig 4 Ref 17 and Para [0102]) for the memory controller; receiving, at the repair circuit of the volatile memory device, an indication (see Fig 5A Ref In and Para [0098]) of a malfunctioning memory address (see Para [0098]) in the volatile memory device; and enabling an address matching register of the repair circuit (see Fig 5 Ref LATCH and Para [0105]) in the volatile memory device, wherein the address matching register corresponds to the malfunctioning memory address (see Para [0105]).
As to claim 3, Dono discloses the method of claim 2, wherein
the control signal is further to indicate that subsequent control signals sent from the memory controller when in the repair mode of operation refer to programming the address matching register of the repair circuit in the volatile memory device (see Para [0091]).
As to claim 4, Dono discloses the method of claim 2, wherein
the volatile memory device comprises primary data storage elements (see Fig 4 Ref 11) and redundant data storage elements (see Fig 4 Refs 11a-1, 11a-2, and 11b).
As to claim 5, Dono discloses the method of claim 4, wherein
the indication of the malfunctioning memory address in the volatile memory device comprises an indication of a row address of the primary data storage elements (see Para [0098]).
As to claim 6, Dono discloses the method of claim 4, further comprising:
receiving, at the repair circuit of the volatile memory device, a set pulse signal (see Fig 5A Ref Err) from the memory controller, wherein
the set pulse signal is generated in response to a memory access instruction (see Para [0152]).
As to claim 7, Dono discloses the method of claim 6, wherein
the memory access instruction comprises at least one of a read instruction, a write instruction, or a row activate instruction (see Para [0018]).
As to claim 8, Dono discloses the method of claim 6, further comprising:
rerouting the memory access instruction directed to the malfunctioning memory address to a corresponding one of the redundant data storage elements (see Para [0026]).
As to claim 9, Dono discloses a volatile memory device (see Fig 4) comprising:
a plurality of data storage elements (see Fig 4 Ref 11); and a programmable repair circuit (see Fig 4 Refs 110A and 110B) coupled to the plurality of data storage elements, the programmable repair circuit to perform operations comprising:
receiving a control signal (see Fig 4 Reds In and In’) from a memory controller (see Fig 4 Refs 12, 16, 17, 18, and 21), the control signal to indicate a repair mode of operation (see Fig 4 Ref 17 and Para [0102]) for the memory controller; receiving an indication (see Fig 5A Ref In and Para [0098]) of a malfunctioning memory address (see Para [0098]) in the volatile memory device; and enabling an address matching register of the programmable repair circuit (see Fig 5 Ref LATCH and Para [0105]) in the volatile memory device, wherein the address matching register corresponds to the malfunctioning memory address (see Para [0105]).
As to claim 10, Dono discloses volatile memory device of claim 9.
Claim 10 recites substantially the same limitations as claim 3.
All the limitations of claim 10 have already been disclosed by Dono in claim 3 above.
As to claim 11, Dono discloses volatile memory device of claim 9.
Claim 11 recites substantially the same limitations as claim 4.
All the limitations of claim 11 have already been disclosed by Dono in claim 4 above.
As to claim 12, Dono discloses volatile memory device of claim 11.
Claim 12 recites substantially the same limitations as claim 5.
All the limitations of claim 12 have already been disclosed by Dono in claim 5 above.
As to claim 13, Dono discloses volatile memory device of claim 11.
Claim 13 recites substantially the same limitations as claim 6.
All the limitations of claim 13 have already been disclosed by Dono in claim 6 above.
As to claim 14, Dono discloses volatile memory device of claim 13.
Claim 14 recites substantially the same limitations as claim 7.
All the limitations of claim 14 have already been disclosed by Dono in claim 7 above.
As to claim 15, Dono discloses volatile memory device of claim 13.
Claim 15 recites substantially the same limitations as claim 8.
All the limitations of claim 15 have already been disclosed by Dono in claim 8 above.
As to claim 16, Dono discloses a system (see Fig 4) comprising:
a memory controller (see Fig 4 Refs 12, 16, 17, 18, and 21); a volatile memory device (see Fig 4 Ref 11) coupled to the memory controller, wherein
the volatile memory device comprises: a plurality of data storage elements (see Fig 4 Ref 11); and a programmable repair circuit (see Fig 4 Refs 110A and 110B) coupled to the plurality of data storage elements,
the programmable repair circuit to perform operations comprising: receiving a control signal (see Fig 4 Reds In and In’) from a memory controller, the control signal to indicate a repair mode of operation (see Fig 4 Ref 17 and Para [0102]) for the memory controller; receiving an indication (see Fig 5A Ref In and Para [0098]) of a malfunctioning memory address (see Para [0098]) in the volatile memory device; and enabling an address matching register of the programmable repair circuit (see Fig 5 Ref LATCH and Para [0105]) in the volatile memory device, wherein the address matching register corresponds to the malfunctioning memory address (see Para [0105]).
As to claim 17, Dono discloses volatile memory device of claim 16.
Claim 17 recites substantially the same limitations as claim 3.
All the limitations of claim 17 have already been disclosed by Dono in claim 3 above.
As to claim 18, Dono discloses volatile memory device of claim 16.
Claim 18 recites substantially the same limitations as claim 4.
All the limitations of claim 18 have already been disclosed by Dono in claim 4 above.
As to claim 19, Dono discloses volatile memory device of claim 18.
Claim 19 recites substantially the same limitations as claim 5.
All the limitations of claim 19 have already been disclosed by Dono in claim 5 above.
As to claim 20, Dono discloses volatile memory device of claim 18.
Claim 19 recites substantially the same limitations as claims 6 and 7.
All the limitations of claim 19 have already been disclosed by Dono in claims 6 and 7 above.
As to claim 21, Dono discloses volatile memory device of claim 20.
Claim 21 recites substantially the same limitations as claim 8.
All the limitations of claim 21 have already been disclosed by Dono in claim 8 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 08/17/2026
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