DETAILED ACTION
This action is responsive to the following communications: the Application filed on January 13, 2025, the Foreign Priority papers retrieved on September 26, 2024, and the Information Disclosure Statements filed on January 13, 2025 and June 11, 2025.
Claims 1-18 are pending. Claims 1 and 10 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDSs) filed on January 13, 2025 and June 11, 2025. These IDSs have been considered.
Specification
The specification is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
In paragraph [0016], lines 4-5, “the dummy word line DWLD, is disposed between the first conductor 230_1, which is coupled to the word line WL1, and the third conductor 250_1” should be --the dummy word line DWLD, is disposed between the first conductor 230_31, which is coupled to the word line WL31, and the third conductor 250_1--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Claims 1-3 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagao et al. (US 20070147117).
Regarding independent claim 1, Nagao et al. disclose a flash memory apparatus [see Fig. 1, para. 22], comprising:
a memory array [Fig. 1: 1, para. 22], comprising a plurality of memory blocks [see Fig. 2, m memory cell array blocks BLKk (k=0 to m-1), para. 25]; and
a memory control circuit [Fig. 1: 6, para. 24], coupled to the memory array and configured to pull an erase voltage applied to a target memory block of the plurality of memory blocks from a reference voltage value up to an erase voltage value during an erase operation [data erasing of a memory cell array is performed per block unit, para. 27. Data erasing per block unit of a memory cell array is performed by changing the voltage of word lines within a presently selected block (selected block) and a p-type well of substrate, para. 28. See Fig. 7(b), at the timing T2, an erase voltage (of about 20 V) is supplied to the p-type well of the plane from the ground, para. 40-41], and after an erase time [see Fig. 7(b), between the timing T2 and the timing T4, in the selected block, electrons of the floating gate of the memory cell are discharged to the p-type well region, so that data per block unit is erased, para. 42], reduce the erase voltage from the erase voltage value in two discharge stages [see Fig. 7(b), at the timing t4, discharge of the erase voltage is launched as a slow discharge, para. 46. This slow discharge is the beginning of the first discharge period, para. 51. At the timing t5, the discharge gradient is strengthened into a rapid discharge, para. 46. This rapid discharge is the beginning of the second discharge period, para. 52. Thus, the discharge operation of the erase voltage (of about 20 V) which is supplied to the p-type well is divided into 2 stages of first and second discharge periods, the first of which is set to be a weak discharge period which becomes a moderate discharge gradient and the second of which is set to be a strong discharge period which becomes an acute discharge gradient after a constant time has elapsed, para. 53].
Regarding claim 2, Nagao et al. disclose wherein the memory control circuit reduces the erase voltage from the erase voltage value to a pass voltage value in a first discharge stage [see Examiner Markup Nagao et al.’s Figure 7(b), erase voltage is discharged to V1 in the first discharge period], and reduces the erase voltage from the pass voltage value to the reference voltage value in a second discharge stage [see Examiner Markup Nagao et al.’s Figure 7(b), V-1 is discharged to V2 in the second discharge period], wherein the erase voltage value is greater than the pass voltage value, and the pass voltage value is greater than the reference voltage value [see Examiner Markup Nagao et al.’s Figure 7(b)].
Regarding claim 3, Nagao et al. disclose wherein a range of a first discharge time spent in the first discharge stage is between 0.01 times a block erase time and 1 times the block erase time [see Fig. 7(b), T4-T5 interval is smaller than T2-T4 interval], and a second discharge time spent in the second discharge stage is less than 1 times the block erase time [see Fig. 7(b), T5-T6 interval is smaller than T2-T4 interval].
Regarding independent claim 10, Nagao et al. disclose an erasing method for a flash memory apparatus [see Fig. 8, para. 46], comprises a plurality of memory blocks [see Fig. 2, m memory cell array blocks BLKk (k=0 to m-1), para. 25], the erasing method comprising:
pulling an erase voltage applied to a target memory block of the plurality of memory blocks from a reference voltage value up to an erase voltage value during an erase operation [data erasing of a memory cell array is performed per block unit, para. 27. Data erasing per block unit of a memory cell array is performed by changing the voltage of word lines within a presently selected block (selected block) and a p-type well of substrate, para. 28. See Fig. 7(b), at the timing T2, an erase voltage (of about 20 V) is supplied to the p-type well of the plane from the ground, para. 40-41]; and
after an erase time [see Fig. 7(b), between the timing T2 and the timing T4, in the selected block, electrons of the floating gate of the memory cell are discharged to the p-type well region, so that data per block unit is erased, para. 42], reducing the erase voltage from the erase voltage value in two discharge stages [see Fig. 7(b), at the timing t4, discharge of the erase voltage is launched as a slow discharge, para. 46. This slow discharge is the beginning of the first discharge period, para. 51. At the timing t5, the discharge gradient is strengthened into a rapid discharge, para. 46. This rapid discharge is the beginning of the second discharge period, para. 52. Thus, the discharge operation of the erase voltage (of about 20 V) which is supplied to the p-type well is divided into 2 stages of first and second discharge periods, the first of which is set to be a weak discharge period which becomes a moderate discharge gradient and the second of which is set to be a strong discharge period which becomes an acute discharge gradient after a constant time has elapsed, para. 53].
Regarding claim 11, Nagao et al. disclose wherein reducing the erase voltage from the erase voltage value in the two discharge stages after the erase time comprises:
reducing the erase voltage from the erase voltage value to a pass voltage value in a first discharge stage [see Examiner Markup Nagao et al.’s Figure 7(b), erase voltage is discharged to V1 in the first discharge period]; and
reducing the erase voltage from the pass voltage value to the reference voltage value in a second discharge stage [see Examiner Markup Nagao et al.’s Figure 7(b), V-1 is discharged to V2 in the second discharge period], wherein the erase voltage value is greater than the pass voltage value, and the pass voltage value is greater than the reference voltage value [see Examiner Markup Nagao et al.’s Figure 7(b)].
Regarding claim 12, Nagao et al. disclose wherein a range of a first discharge time spent in the first discharge stage is between 0.01 times a block erase time and 1 times the block erase time [see Fig. 7(b), T4-T5 interval is smaller than T2-T4 interval], and a second discharge time spent in the second discharge stage is less than 1 times the block erase time [see Fig. 7(b), T5-T6 interval is smaller than T2-T4 interval].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-9 and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nagao et al. (US 20070147117) as applied to claims 1 and 10 above, in view of Dutta et al. (US 20130314995).
Regarding claim 4, Nagao et al. teach the limitations with respect to claim 1.
Furthermore, Nagao et al. disclose wherein the target memory block comprises:
a first well region [Fig. 3: 10], having a second conductivity type [n-type];
a second well region [Fig. 3: 11], having the first conductivity type [p-type] and disposed on the first well region [see Fig. 3];
a plurality of first conductors, disposed on the second well region and configured to be respectively coupled to a plurality of word lines [see Fig. 3, WL0-WL15];
two third conductors, disposed at a position where the second well region is adjacent to the substrate, and configured to be respectively coupled to a first select gate line and a second select gate line [see Fig. 3, SGS, SGD]; and
two fourth conductors, disposed on a doped region in a surface region of the substrate, and configured to be respectively coupled to a bit line and a source line [see Fig. 3: 17, 18, a common source line (CELSRC) 17 inside the block BLKk, which is embedded within an inner section of the interlayer insulation film 16, contacts with a source diffusion layer 13b of the one selection gate transistor S1. The bit line (BL) 18 formed on the interlayer insulation film 16 comes into contact with the drain diffusion layer 13a of the other selection gate transistor. These contacts of the source line 17 and the bit lines 18 are shared in the adjacent NAND cells, para. 29].
However, Nagao et al. are silent with respect to disclose a substrate, having a first conductivity type and a plurality of second conductors, disposed on the second well region and configured to be respectively coupled to a plurality of dummy word lines.
Dutta et al. teach a memory block [see Fig. 1C] comprises:
a substrate, having a first conductivity type [Fig. 1C: 144, a p-type substrate 144, para. 42];
a first well region [Fig. 1C: 142], having a second conductivity type and disposed on the substrate [see Fig. 1C, an n-well region 142 is disposed on the substrate 144, para. 42];
a second well region [Fig. 1: 140], having the first conductivity type and disposed on the first well region [see Fig. 1C, a p-well region 140 is disposed on the n-well region 142, para. 42];
a plurality of first conductors, disposed on the second well region and configured to be respectively coupled to a plurality of word lines [see Fig. 1C, the transistors of the NAND string are formed in p-well region 140. Each transistor includes a stacked gate structure that consists of a control gate (100CG, 102CG, 104CG and 106CG) and a floating gate (100FG, 102FG, 104FG and 106FG). The control gates of the memory cells (100, 102, 104 and 106) form the word lines, para. 42];
a plurality of second conductors, disposed on the second well region and configured to be respectively coupled to a plurality of dummy word lines [see Fig. 1C with respect to Fig. 2, the control gates of the memory cells (100, 102, 104 and 106) form the word lines, para. 42. A block of NAND flash memory cells which includes one drain-side dummy word line WLDD0 and one source-side dummy word line WLDS0, para. 49];
two third conductors, disposed at a position where the second well region is adjacent to the substrate, and configured to be respectively coupled to a first select gate line and a second select gate line [see Fig. 1B, select gate 120 connects the NAND string to bit line 126 and is connected to select line SGD. Select gate 122 connects the NAND string to source line 128 and is connected to select line SGS, para. 41. The transistors of the NAND string are formed in p-well region 140, para. 42]; and
two fourth conductors, disposed on a doped region in a surface region of the substrate, and configured to be respectively coupled to a bit line and a source line [see Fig. 1C, N+ doped layer 126 connects to the bit line for the NAND string, while N+ doped layer 128 connects to a common source line for multiple NAND strings, para. 42].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dutta et al. to the teachings of Nagao et al. such that using known NAND block structure of Dutta et al. in Nagao et al.’s erase operation because both references are directed to NAND flash erase operations and deal with problems caused by high erase voltages and capacitive coupling, thereby this combination would improve erase reliability and endurance in NAND flash.
Regarding claim 5, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 4.
Furthermore, Dutta et al. disclose wherein in a planar direction, the second conductor coupled to the dummy word line is configured between the first conductor coupled to the word line and the third conductor [see Fig. 2, source-side dummy word line WLDS0 is adjacent to source select gate line SGS and drain-side dummy word line WLDD0 is adjacent to drain select gate line SGD. There are also word lines between the drain-side dummy word line WLDD0 and the source-side dummy word line WLDS0, para. 49].
Regarding claim 6, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 4.
Furthermore, Dutta et al. disclose wherein during the erase operation, the bit line and the source line are in a floating state [memory cells are erased in one embodiment by raising the p-well to an erase voltage (e.g., 20 V) for a sufficient period of time and grounding or applying a low bias, e.g., 1 V, on the word lines of a selected block while the source and bit lines are floating, para. 57], and the first select gate line and the second select gate line are in the floating state after being pulled up to a select voltage value [Vsgs/sgd_array is driving to a specified initial zero or non-zero level, e.g., 2V, then floating Vsgs/sgd_array while subsequently increasing Vp-well, para. 90].
Regarding claim 7, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 4.
Furthermore, Nagao et al. disclose wherein during the erase operation, the memory control circuit applies the erase voltage to the second well region [an erase voltage (of about 20 V) is supplied to the p-type well of the plane, para. 41].
Regarding claim 8, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 4.
Furthermore, Dutta et al. disclose wherein during the erase operation, a potential of the source line, the first select gate line, and the second select gate line changes with a potential of the second well region due to a coupling effect [due to capacitive coupling, the unselected word lines, bit lines, select lines, and common source are also raised to a significant fraction of the erase voltage, para. 57. During an erase operation, increasing the p-well/substrate voltage causes an electromagnetic field which is capacitively coupled from the substrate to the select gate transistors and the storage elements, raising their potentials when floated, para. 62].
Regarding claim 9, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 4.
Furthermore, Dutta et al. disclose wherein the first conductivity type is P- type, and the second conductivity type is N-type [see Fig. 1C, p-well region 140 and n-well region 142, para. 42].
Regarding claim 13, Nagao et al. teach the limitations with respect to claim 10.
Furthermore, Nagao et al. disclose wherein the target memory block comprises:
a first well region [Fig. 3: 10], having a second conductivity type [n-type];
a second well region [Fig. 3: 11], having the first conductivity type [p-type] and disposed on the first well region [see Fig. 3];
a plurality of first conductors, disposed on the second well region and configured to be respectively coupled to a plurality of word lines [see Fig. 3, WL0-WL15];
two third conductors, disposed at a position where the second well region is adjacent to the substrate, and configured to be respectively coupled to a first select gate line and a second select gate line [see Fig. 3, SGS, SGD]; and
two fourth conductors, disposed on a doped region in a surface region of the substrate, and configured to be respectively coupled to a bit line and a source line [see Fig. 3: 17, 18, a common source line (CELSRC) 17 inside the block BLKk, which is embedded within an inner section of the interlayer insulation film 16, contacts with a source diffusion layer 13b of the one selection gate transistor S1. The bit line (BL) 18 formed on the interlayer insulation film 16 comes into contact with the drain diffusion layer 13a of the other selection gate transistor. These contacts of the source line 17 and the bit lines 18 are shared in the adjacent NAND cells, para. 29].
However, Nagao et al. are silent with respect to disclose a substrate, having a first conductivity type and a plurality of second conductors, disposed on the second well region and configured to be respectively coupled to a plurality of dummy word lines.
Dutta et al. teach a memory block [see Fig. 1C] comprises:
a substrate, having a first conductivity type [Fig. 1C: 144, a p-type substrate 144, para. 42];
a first well region [Fig. 1C: 142], having a second conductivity type and disposed on the substrate [see Fig. 1C, an n-well region 142 is disposed on the substrate 144, para. 42];
a second well region [Fig. 1: 140], having the first conductivity type and disposed on the first well region [see Fig. 1C, a p-well region 140 is disposed on the n-well region 142, para. 42];
a plurality of first conductors, disposed on the second well region and configured to be respectively coupled to a plurality of word lines [see Fig. 1C, the transistors of the NAND string are formed in p-well region 140. Each transistor includes a stacked gate structure that consists of a control gate (100CG, 102CG, 104CG and 106CG) and a floating gate (100FG, 102FG, 104FG and 106FG). The control gates of the memory cells (100, 102, 104 and 106) form the word lines, para. 42];
a plurality of second conductors, disposed on the second well region and configured to be respectively coupled to a plurality of dummy word lines [see Fig. 1C with respect to Fig. 2, the control gates of the memory cells (100, 102, 104 and 106) form the word lines, para. 42. A block of NAND flash memory cells which includes one drain-side dummy word line WLDD0 and one source-side dummy word line WLDS0, para. 49];
two third conductors, disposed at a position where the second well region is adjacent to the substrate, and configured to be respectively coupled to a first select gate line and a second select gate line [see Fig. 1B, select gate 120 connects the NAND string to bit line 126 and is connected to select line SGD. Select gate 122 connects the NAND string to source line 128 and is connected to select line SGS, para. 41. The transistors of the NAND string are formed in p-well region 140, para. 42]; and
two fourth conductors, disposed on a doped region in a surface region of the substrate, and configured to be respectively coupled to a bit line and a source line [see Fig. 1C, N+ doped layer 126 connects to the bit line for the NAND string, while N+ doped layer 128 connects to a common source line for multiple NAND strings, para. 42].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Dutta et al. to the teachings of Nagao et al. such that using known NAND block structure of Dutta et al. in Nagao et al.’s erase operation because both references are directed to NAND flash erase operations and deal with problems caused by high erase voltages and capacitive coupling, thereby this combination would improve erase reliability and endurance in NAND flash.
Regarding claim 14, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 13.
Furthermore, Dutta et al. disclose wherein in a planar direction, the second conductor coupled to the dummy word line is configured between the first conductor coupled to the word line and the third conductor [see Fig. 2, source-side dummy word line WLDS0 is adjacent to source select gate line SGS and drain-side dummy word line WLDD0 is adjacent to drain select gate line SGD. There are also word lines between the drain-side dummy word line WLDD0 and the source-side dummy word line WLDS0, para. 49].
Regarding claim 15, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 13.
Furthermore, Dutta et al. disclose wherein during the erase operation, the bit line and the source line are in a floating state [memory cells are erased in one embodiment by raising the p-well to an erase voltage (e.g., 20 V) for a sufficient period of time and grounding or applying a low bias, e.g., 1 V, on the word lines of a selected block while the source and bit lines are floating, para. 57], and the first select gate line and the second select gate line are in the floating state after being pulled up to a select voltage value [Vsgs/sgd_array is driving to a specified initial zero or non-zero level, e.g., 2V, then floating Vsgs/sgd_array while subsequently increasing Vp-well, para. 90].
Regarding claim 16, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 13.
Furthermore, Nagao et al. disclose wherein during the erase operation, the erase voltage is applied to the second well region [an erase voltage (of about 20 V) is supplied to the p-type well of the plane, para. 41].
Regarding claim 17, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 13.
Furthermore, Dutta et al. disclose wherein during the erase operation, a potential of the source line, the first select gate line, and the second select gate line changes with a potential of the second well region due to a coupling effect [due to capacitive coupling, the unselected word lines, bit lines, select lines, and common source are also raised to a significant fraction of the erase voltage, para. 57. During an erase operation, increasing the p-well/substrate voltage causes an electromagnetic field which is capacitively coupled from the substrate to the select gate transistors and the storage elements, raising their potentials when floated, para. 62].
Regarding claim 18, Nagao et al. in combination with Dutta et al. teach the limitations with respect to claim 13.
Furthermore, Dutta et al. disclose wherein the first conductivity type is P- type, and the second conductivity type is N-type [see Fig. 1C, p-well region 140 and n-well region 142, para. 42].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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