DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 3 and 5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4 and 6 of U.S. Patent No. 12,266,392. Although the claims at issue are not identical, they are not patentably distinct from each other because each and every limitation claimed herein has in fact been claimed and patented. Namely:
Pending claim 2 corresponds to patented claim 1.
Pending claim 3 corresponds to patented claim 6.
Pending claim 5 corresponds to patented claim 4.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2 – 5 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Slesazeck et al. (US Pat Pub 11,205,467).
Regarding claim 2, Slesazeck et al. disclose a semiconductor device (for example figs. 1 – 15 and all related texts) comprising:
a cell (for example fig. 6a. See also col. 13, lines 62 – 65) comprising a capacitor (ferroelectric capacitor C1), a first transistor(T4), and a second transistor (T3), wherein the capacitor comprises a first electrode (connected to node n1), a second electrode (connected to plateline PL), and a ferroelectric layer between the first electrode and the second electrode (see col. 4, lines 12 – 31),
wherein one of a source and a drain of the first transistor is electrically connected to the first electrode of the capacitor and a gate of the second transistor (source of T4 connects to gate of T3 and first electrode of C1 at node n1, fig. 6a),
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring (source of T4 connects to bit line BL),
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring (source of T3 also connects to bit line BL),
wherein data is written to the cell through the first wiring (which is bit line BL, through which data is written to the ferroelectric capacitor C1, fig. 6a), and
wherein the data retained in the cell is read through the first wiring (data is also read through bit line BL. See further col. 14, lines 10 – 18).
Regarding claim 3, Slesazeck et al. also disclose the semiconductor device according to the semiconductor device according to claim 2 (fig. 6a and all related texts), wherein the other of the source and the drain of the second transistor (T3) is electrically connected to a second wiring (drain of T3), and wherein the second wiring is supplied with a constant potential (which is ground potential as shown in fig. 6a).
Regarding claim 4, Slesazeck et al. also disclose the semiconductor device according to the semiconductor device according to claim 2 (fig. 6a and all related texts) wherein a gate of the first transistor (T4) is electrically connected to a third wiring (which is word line WL), and wherein the second electrode of the capacitor is electrically connected to a fourth wiring (which is plate line PL).
Regarding claim 5, Slesazeck et al. also disclose the semiconductor device according to claim 2, wherein the first transistor comprises a metal oxide in a channel formation region (considered inherent given the T4 and T3 of fig. 6a are MOSFET type transistors, i.e. the terminals are referred to as source/drain/gate. See further “n-channel” transistors, col. 1, lines 53 – 63).
Allowable Subject Matter
Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the semiconductor device according to claim 2 above, further comprising, in combination, the features and limitations additionally claimed at least in claim 6 or 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LY D PHAM/Primary Examiner, Art Unit 2827 August 26, 2026
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