DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12243589. Although the claims at issue are not identical, they are not patentably distinct from each other because at least independent claims are rejected as shown in a table below.
Instant app
Patent 12243589
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750
908
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Greyscale
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570
728
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Greyscale
Claim 11
Claim 1/10
Claim 17
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198
410
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Greyscale
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353
395
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Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sarkar et al. (PGPUB 20110051507), hereinafter as Sarkar, in view of Murata (PGPUB 20110205815), hereinafter as Murata.
Regarding claim 17, Sarkar teaches a method, comprising:
during a first operation, each one of a plurality of memory cells receiving a first voltage signal (Fig 3, voltage 320) through a control line and receiving a second voltage signal through at least one of a data line or a source line (Fig 1, 105 bit line and line connected to 120);
providing a first reference voltage signal by a header unit or providing a second reference voltage signal by a footer unit;
transmitting the first reference voltage signal or the second reference voltage signal as the first voltage signal to the plurality of memory cells by a transmission unit coupled in series with the at least one of the header unit or the footer unit; and
during a second operation, at least one of the plurality of memory cells receiving a third voltage signal, wherein the third voltage signal oscillates between a positive voltage level and a negative voltage level, wherein the positive voltage level is higher than the first reference voltage signal (Fig 4, voltage 420) or the negative voltage level is lower than the second reference voltage signal (not being considered, refereeing to: MPEP 2111.04 II, contingent limitations, for a method claim, a condition method/process, only one condition need to be considered),
but not expressly transmission unit, a heater/foot units,
Murata teaches providing a first reference voltage signal (Fig. 2 VWLX) by a header unit (Fig 2, P2) or providing a second reference voltage signal by a footer unit (an option not being considered for a method claim);
transmitting the first reference voltage signal or the second reference voltage signal as the first voltage signal to the plurality of memory cells by a transmission unit (Fig. 2, P30 and P30A) coupled in series with the at least one of the header unit or the footer unit.
Since Murata and Sarkar are both from the same field of semiconductor memory device, the purpose disclosed by Murata would have been recognized in the pertinent art of Sarkar.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use circuits as in Murata into the device of Sarkar for the purpose of providing working voltages for the memory device.
Regarding claim 18, Sarkar teaches when every time period elapses, performing the second recover operation ([0026]maintenance process may be based on a predetermined time schedule).
Regarding claim 19, Sarkar teaches detecting a current change associated with at least one of the data line or the source line; and when the current change exceeds a threshold value, performing the second recover operation ([0026]based on detecting errors).
Regarding claim 20, Sarkar teaches monitoring the current change while performing the second recover operation; and
when the current change is equal to or lower than the threshold value, performing the first normal operation (Fig 6, step 660).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827
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