DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-17 are objected to because of the following informalities:
Regarding claim 1: To correct grammar, it is suggested to change “a control terminal of the first transistor” to “wherein a control terminal of the first transistor”, and to change ”the total transistor size of the conducted transistors in the first circuit device,” to ”the total transistor size of the conducted transistors in the first circuit device, and”. Also, “and” should be added after “a trimming operation;”.
Regarding claim 3: It is indefinite as to whether “a mismatch” is the same mismatch already claimed in claim 1.
Regarding claim 11: To correct grammar, it is suggested to change “a control terminal of the first transistor” to “wherein a control terminal of the first transistor”, and to change ”the total transistor size of the conducted transistors in the first circuit device,” to ”the total transistor size of the conducted transistors in the first circuit device, and”. Also, “and” should be added after “a trimming operation;”.
Regarding claim 13: It is indefinite as to whether “a mismatch” is the same mismatch already claimed in claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1: There is insufficient antecedent basis for “the mismatch between the first voltage and the second voltage”. Claims 2-10 depend on claim 1.
When also considering the objections above, Examiner suggests amending the claim as follows:
Claim 1: A memory device, comprising:
a memory array with a first memory cell and a second reference memory cell; and
a memory cell read circuit, comprising:
a first branch, comprising a first circuit device, configured to output a first voltage to the second reference memory cell in a trimming operation; and
a second branch, comprising a second circuit device, configured to output a second voltage to the first memory cell in the trimming operation,
wherein the first circuit device comprises a first transistor and a plurality of second transistors coupled to the first transistor, wherein a control terminal of the first transistor and control terminals of the plurality of second transistors are biased by a fixed clamp voltage,
wherein the second circuit device comprises a third transistor and a plurality of fourth transistors that are coupled to the third transistor, wherein a control terminal of the third transistor and control terminals of the plurality of fourth transistors are biased by the fixed clamp voltage,
wherein each of the plurality of second transistors, when individually conducted, is configured to adjust a total transistor size of conducted transistors in the first circuit device by a second percentage of the total transistor size of the conducted transistors in the first circuit device,
the plurality of second transistors include a first number of conducted trimming transistors, and
the first number of conducted trimming transistors is determined according to the second percentage of the total transistor size of the conducted transistors in the first circuit device and a change of the total transistor size of the conducted transistors in the first circuit device, and
wherein the change of the total transistor size of the conducted transistors in the first circuit device is determined according to a mismatch between the first voltage and the second voltage.
Regarding claim 3: It is indefinite as to whether “a mismatch” is to refer to the mismatch already referred to in claim 1.
Regarding claim 11: There is insufficient antecedent basis for each of the following limitations:
“the reference memory cell”;
“the first clamp transistor”; and
“the mismatch between the first voltage and the second voltage”.
Claims 12-17 depend on claim 11.
When also considering the objections above, Examiner suggests amending the claim as follows:
Claim 11: A memory cell read circuit, comprising:
a first branch, comprising a first circuit device, configured to output a first voltage to a reference memory cell in a trimming operation; and
a second branch, comprising a second circuit device, configured to output a second voltage to a memory cell in the trimming operation,
wherein the first circuit device comprises a first transistor and a plurality of second transistors coupled to the first wherein a control terminal of the first transistor and control terminals of the plurality of second transistors are biased by a fixed clamp voltage,
wherein the second circuit device comprises a third transistor and a plurality of fourth transistors that are coupled to the third transistor, wherein a control terminal of the third transistor and control terminals of the plurality of fourth transistors are biased by the fixed clamp voltage,
wherein each of the plurality of second transistors, when individually conducted, is configured to adjust a total transistor size of conducted transistors in the first circuit device by a second percentage of the total transistor size of the conducted transistors in the first circuit device,
the plurality of second transistors include a first number of conducted trimming transistors, and
the first number of conducted trimming transistors is determined according to the second percentage of the total transistor size of the conducted transistors in the first circuit device and a change of the total transistor size of the conducted transistors in the first circuit device, and wherein the change of the total transistor size of the conducted transistors in the first circuit device is determined according to a mismatch between the first voltage and the second voltage.
Regarding claim 13: It is indefinite as to whether “a mismatch” is to refer to the mismatch already referred to in claim 11.
Regarding claim 20: It is indefinite as to whether “a mismatch” is to refer to the mismatch already referred to in claim 18 or a different one.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11, 13, 14, and 17-20 of U.S. Patent No. 12,230,352 (US 12,230,352). Although the claims at issue are not identical, they are not patentably distinct from each other because of the following:
Regarding claim 1: In so far as definite, Claim 1 of US 12,230,352 teaches a memory device, comprising:
a memory array with a first memory cell (“a memory cell”) and a second reference memory cell (“a reference memory cell”); and
a memory cell read circuit, comprising:
a first branch, comprising a first circuit device, configured to output a first voltage to the second reference memory cell in a trimming operation; and
a second branch, comprising a second circuit device, configured to output a second voltage to the first memory cell in the trimming operation,
wherein the first circuit device comprises a first transistor and a plurality of second transistors coupled to the first transistor, wherein a control terminal of the first transistor and control terminals of the plurality of second transistors are biased by a fixed clamp voltage,
wherein the second circuit device comprises a third transistor and a plurality of fourth transistors that are coupled to the third transistor, wherein a control terminal of the third transistor and control terminals of the plurality of fourth transistors are biased by the fixed clamp voltage,
wherein each of the plurality of second transistors, when individually conducted, is configured to adjust a total transistor size of conducted transistors in the first circuit device by a second percentage of the total transistor size of the conducted transistors in the first circuit device,
the plurality of second transistors include a first number of conducted trimming transistors, and
the first number of conducted trimming transistors is determined according to the second percentage of the total transistor size of the conducted transistors in the first circuit device and a change of the total transistor size of the conducted transistors in the first circuit device, and
wherein the change of the total transistor size of the conducted transistors in the first circuit device is determined according to a mismatch between the first voltage and the second voltage.
Regarding claim 2: Claim 2 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 3: Claim 3 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 4: Claim 4 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 5: Claim 5 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 6: Claim 6 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 7: Claim 1 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 8: Claim 7 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 9: Claim 8 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 10: Claim 8 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 11: In so far as definite, Claim 9 of US 12,230,352 teaches a memory cell read circuit, comprising:
a first branch, comprising a first circuit device, configured to output a first voltage to the reference memory cell in a trimming operation;
a second branch, comprising a second circuit device, configured to output a second voltage to the memory cell in the trimming operation,
wherein the first circuit device comprises a first transistor and a plurality of second transistors coupled to the first clamp transistor (“the first transistor”), a control terminal of the first transistor and control terminals of the plurality of second transistors are biased by a fixed clamp voltage,
wherein the second circuit device comprises a third transistor and a plurality of fourth transistors that are coupled to the third transistor, wherein a control terminal of the third transistor and control terminals of the plurality of fourth transistors are biased by the fixed clamp voltage,
wherein each of the plurality of second transistors, when individually conducted, is configured to adjust a total transistor size of conducted transistors in the first circuit device by a second percentage of the total transistor size of the conducted transistors in the first circuit device,
the plurality of second transistors include a first number of conducted trimming transistors, and
the first number of conducted trimming transistors is determined according to the second percentage of the total transistor size of the conducted transistors in the first circuit device and a change of the total transistor size of the conducted transistors in the first circuit device, wherein the change of the total transistor size of the conducted transistors in the first circuit device is determined according to the mismatch between the first voltage and the second voltage.
Regarding claim 12: Claim 10 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 13: Claim 11 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 14: Claim 14 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 15: Claim 13 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 16: Claim 9 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 17: Claim 17 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 18: Claim 18 of US 12,230,352 teaches a control method of compensating a mismatch between a first voltage and a second voltage in a memory cell read circuit, the memory cell read circuit comprises a first circuit device and a second circuit device, the first circuit device comprises a first transistor and a plurality of second transistors, and the second circuit device comprises a third transistor and a plurality of fourth transistors, the method comprising:
determining the mismatch between the first voltage and the second voltage in the memory cell read circuit;
selecting a first number of second transistors from the plurality of second transistors that is coupled to the first transistor according to the mismatch between the first voltage and the second voltage;
selecting a second number of fourth transistors from the plurality of fourth transistors that is coupled to the second transistor according to the mismatch between the first voltage and the second voltage,
biasing a control terminal of the first transistor and control terminals of the plurality of second transistors with a fixed clamp voltage;
biasing a control terminal of the third transistor and control terminals of the plurality of fourth transistors with the fixed clamp voltage; and
conducting the first number of the second transistors and the second number of fourth transistors,
wherein each of the plurality of second transistors, when individually conducted, is configured to adjust a total transistor size of conducted transistors in the first circuit device by a second percentage of the total transistor size of the conducted transistors in the first circuit device,
the plurality of second transistors include a first number of conducted trimming transistors, and
the first number of conducted trimming transistors is determined according to the second percentage of the total transistor size of the conducted transistors in the first circuit device and a change of the total transistor size of the conducted transistors in the first circuit device, wherein the change of the total transistor size of the conducted transistors in the first circuit device is determined according to the mismatch between the first voltage and the second voltage.
Regarding claim 19: Claim 19 of US 12,230,352 teaches the subject matter of this claim.
Regarding claim 20: In so far as definite, Claim 20 of US 12,230,352 teaches the subject matter of this claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
Prosecution Insights