Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed January 16, 2025.
Status of claims to be treated in this office action:
a. Independent: 1, 10, 16
b. Pending: 1-20
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Di et al. (US Pat. 11095287 B1; “Di”) in view of Rezaei et al. (“Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries”; “Rezaei”) and Keskin et al. (US Pub. 20090079483 A1; “Keskin”).
Regarding independent claim 1, Di discloses:
a polymorphic gate (Fig. 3; col. 4, lines 49-50: FIG. 3 is a Boolean NAND-NOR Polymorphic Gate Schematic) comprises:
(i) a low voltage function and a high voltage function (col. 1, lines 40-45: providing multiple polymorphic Multi-Threshold NULL Convention Logic gates that exhibit one function under a higher supply voltage, and the other function under a lower supply voltage and asynchronous polymorphic circuits able to implement two distinctive functionalities controlled by the supply voltage),
(ii) a pull-down network (PDN) that is associated with the high voltage function (col. 7, lines 31-37: In the pull-down network (bottom half), transistor M4 is OFF. Transistors M5 and M6 are ON. When VDD is set to the HIGH voltage (1.2 V), transistor M0 passes a relatively high voltage value to the gate of transistor M7. This effectively allows transistor M7 to be fully ON, creating a strong path to Ground (GND)),
(iii) a pull-up network (PUN) that is coupled to the PDN, wherein the PUN is associated with the low voltage function (col. 7, lines 42-49: When VDD is set to the LOW voltage (0.7 V), transistor M7 is much more sensitive to any voltage reduction coming from transistor M0. Transistor M0 weakens the value of VDD it passes, and the effective resistance transistor M7 provides is increased. This reduces the strength of the path to GND, and allows the pull-up network to overpower the pull-down network and provide a high voltage to the output inverter (transistors M9 and M10)), and
(iv) one or more gating transistors that are configured to provide the PDN with a path to a ground (Fig. 5: transistor M0; col. 7, lines 12-13: Transistors M0 and M7 correspond to the gating mechanism serving as a selective active resistor for the circuit);
Di does not disclose:
a polymorphic latch comprising:
a pair of gates that is configured in a D-latch, wherein a gate of the pair of gates comprises:
a pair of AND logic gates, wherein an output of an AND logic gate of the pair of AND logic gates is coupled to an input of the polymorphic gate; and
an inverter coupled to an input of the AND logic gate.
However, Rezaei teaches:
a polymorphic latch (p.536, left column, four lines from bottom of page: D-type latch) comprising:
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Rezaei to Di wherein there is a polymorphic latch in order to support a hardware obfuscation method using hybrid memristor-CMOS technology (Rezaei, Abstract).
Also, Keskin teaches:
a pair of gates (Fig. 4A: NOR gates 418 and 420; [0031]) that is configured in a D-latch (D latch 410; [0031]), wherein a gate of the pair of gates comprises:
a pair of AND logic gates (AND gates 414 and 416; [0031]), wherein an output of an AND logic gate of the pair of AND logic gates is coupled to an input of the polymorphic gate (the output of AND gate 414 is coupled to an input of NOR gate 418. Examiner asserts that the Boolean NAND-NOR Polymorphic Gate of Di may be substituted for one of the NOR gates of Keskin); and
an inverter (inverter 412; [0031]) coupled to an input of the AND logic gate (414).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Keskin to modified Di wherein there is a pair of gates that is configured in a D-latch, a pair of AND logic gates, wherein an output of an AND logic gate of the pair of AND logic gates is coupled to an input of the gate; and an inverter coupled to an input of the AND logic gate in order to provide delay circuits that match propagation delays of synchronous circuits and that may be used in high-speed digital circuits (Keskin, [0007]).
Regarding claim 5, Di, Rezaei, and Keskin together disclose the limitations of claim 1. Further, through Di:
wherein the low voltage function comprises a function associated with providing a supply voltage (col. 1, lines 40-45) to the pair of polymorphic gates (Fig. 3), wherein the supply voltage is below a threshold voltage (col. 6, lines 54-61: Two supply voltages are chosen such that the lower voltage will significantly weaken the undesirable portions of the pull-down network and cause the function of the polymorphic gate to change. When the higher supply voltage is applied, the threshold drop is not significant enough to weaken the pull-down network, and the other built-in function is in effect. Examiner asserts that there is an unnamed threshold voltage because the lower and higher voltages that are below and above the threshold, respectively, must satisfy the above conditions).
Regarding claim 6, Di, Rezaei, and Keskin together disclose the limitations of claim 1. Further, through Di:
wherein the high voltage function comprises a function associated with providing a supply voltage (col. 1, lines 40-45) to the pair of polymorphic gates (Fig. 3), wherein the supply voltage is above a threshold voltage (col. 6, lines 54-61; see explanation in claim 5 rejection).
Regarding claim 7, Di, Rezaei, and Keskin together disclose the limitations of claim 1. Further, through Di:
polymorphic gates (Fig. 3)
Di does not disclose:
wherein the pair of gates comprises a pair of two bistable feedback gates.
However, Kestin teaches:
wherein the pair of gates (Fig. 4A: 418 & 420) comprises a pair of two bistable feedback gates ([0031]: NOR gates 418 and 420 are cross-coupled in a feedback configuration and have their second inputs coupled to the outputs of NOR gates 420 and 418, respectively).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Keskin to modified Di wherein the pair of gates comprises a pair of two bistable feedback gates in order to provide delay circuits that match propagation delays of synchronous circuits and that may be used in high-speed digital circuits (Keskin, [0007]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Di (US Pat. 11095287 B1), Rezaei (“Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries”), and Keskin (US Pub. 20090079483 A1) as applied to claim 1 above, and further in view of Iwai et al. (US Pub. 20100157693 A1; “Iwai”).
Regarding claim 2, Di, Rezaei, and Keskin together disclose the limitations
of claim 1. Neither Di, Rezaei, nor Keskin discloses:
wherein the low voltage function comprises a NAND gate operation.
However, Iwai teaches:
wherein the low voltage function comprises a NAND gate operation ([0171]: This configuration provides the output from the NAND gate G247 as the low-capacity low-voltage operation mode shift signal LOWMODEIN. Examiner asserts that the NAND of Iwai provides a low voltage function because the output of the NAND is a low-voltage control signal).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Iwai to modified Di wherein the low voltage function comprises a NAND gate operation in order to provide a device with changeable storage capacity and address space required for memory cell access (Iwai, [0008]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Di (US Pat. 11095287 B1), Rezaei (“Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries”), and Keskin (US Pub. 20090079483 A1) as applied to claim 1 above, and further in view of Gupta et al. (US Pub. 20230267992 A1; “Gupta”).
Regarding claim 4, Di, Rezaei, and Keskin together disclose the limitations
of claim 1. Neither Di, Rezaei, nor Keskin discloses:
wherein the high voltage function comprises a NOR gate operation.
However, Gupta teaches:
wherein the high voltage function comprises a NOR gate operation ([0055]: The output transistors form an NOR gate distributed across the bit-storing cells. The circuit includes logic (e.g., in the form of transistor circuit structure) to sustain a high binary voltage level on an output of the NOR gate, on condition that a read signal is applied to the plurality of bit-storing cells and also that a value stored in an evaluated bit-storing cell satisfies a value (e.g., is a “1”). Examiner asserts that the NOR of Gupta provides a high voltage function because the output of the NOR has a high voltage level).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Gupta to modified Di wherein the high voltage function comprises a NOR gate operation in order to provide a NOR gate that acts as an input to a global bitline for a system that provides power and energy savings (Gupta, [0062] & [0121]).
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Keskin (US Pub. 20090079483 A1) in view of Rezaei (“Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries”) and Di (US Pat. 11095287 B1).
Regarding independent claim 10, Keskin discloses a register ([0005]: Multiple flip-flops may be coupled in parallel or in series to form a register for any number of bits) comprising:
a first latch (Fig. 7A: D latch 710a; [0044]) comprising a first data input (input data Din; [0044]) and a first data output (Q output of D latch 710a);
a second latch (D latch 710b) comprising a second data input and a second data output, wherein the first data output is coupled to the second data input ([0044]: D latch 710b…has its D input coupled to the Q output of D latch 710a);
Keskin does not disclose:
a polymorphic register
a polymorphic latch
wherein the first polymorphic latch or the second polymorphic latch comprises a low voltage function and a high voltage function.
However, Rezaei teaches:
a polymorphic register (p. 537, right col., five and six lines from the bottom of the page: connect all FFs in a shift register)
a polymorphic latch (p. 536, left column, four lines from bottom of page: D-type latch)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Rezaei to Keskin wherein there is a polymorphic register and a polymorphic latch in order to support a hardware obfuscation method using hybrid memristor-CMOS technology (Rezaei, Abstract).
Also, Di teaches:
wherein the first polymorphic latch or the second polymorphic latch comprises a low voltage function and a high voltage function (col. 1, lines 40-45 teach that the polymorphic gates comprise low and high voltage functions. Examiner notes that Spec [0008] mentions that a latch comprises a low voltage and high voltage function, but there is no further explanation of this functionality, so Examiner assumes these functions arise from the polymorphic gates within each latch).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Di to modified Keskin wherein the first polymorphic latch or the second polymorphic latch comprises a low voltage function and a high voltage function in order to provide an asynchronous polymorphic circuit that provides two separate functionalities controlled by the supply voltage (Di, col. 3, lines 56-62).
Regarding claim 11, Keskin, Rezaei, and Di together disclose the limitations
of claim 10. Limitations (i) and (ii) of claim 11 are substantially the same as (ii) and (iii) from claim 1, and are thus rejected for the same reasons. Further,
(iii) the first logic gate functionality is different from the second logic gate functionality (Examiner asserts that this is obvious given that the pull-down and pull-up networks of Di, described in col. 7, lines 31-37 and lines 42-49, respectively, are not the same).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Di to modified Keskin wherein the first logic gate functionality is different from the second logic gate functionality in order to provide an asynchronous polymorphic circuit that provides two separate functionalities controlled by the supply voltage (Di, col. 3, lines 56-62).
Regarding claim 12, Keskin, Rezaei, and Di together disclose the limitations
of claim 10. Rezaei teaches a polymorphic latch, and further through Di:
wherein the low voltage function is associated with providing a supply voltage to the first polymorphic latch (col. 7, lines 42-43: When VDD is set to the LOW voltage (0.7 V). Examiner asserts that a TH33m-TH33w2m polymorphic gate receives a low supply voltage. Per the explanation in the rejection of claim 10 above, Examiner assumes the voltage functions arise from the polymorphic gates within each latch) or the second polymorphic latch, wherein the supply voltage is below a threshold voltage.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Di to modified Keskin wherein the low voltage function is associated with providing a supply voltage to the first polymorphic latch or the second polymorphic latch, wherein the supply voltage is below a threshold voltage in order to provide an asynchronous polymorphic circuit that provides two separate functionalities controlled by the supply voltage (Di, col. 3, lines 56-62).
Regarding claim 13, Keskin, Rezaei, and Di together disclose the limitations
of claim 10. Rezaei teaches a polymorphic latch, and further through Di:
wherein the high voltage function is associated with providing a supply voltage to the first polymorphic latch (col. 7, lines 33-34: When VDD is set to the HIGH voltage (1.2 V). See explanation in the rejection of claim 12 above) or the second polymorphic latch, wherein the supply voltage is above a threshold voltage.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Di to modified Keskin wherein the high voltage function is associated with providing a supply voltage to the first polymorphic latch or the second polymorphic latch, wherein the supply voltage is below a threshold voltage in order to provide an asynchronous polymorphic circuit that provides two separate functionalities controlled by the supply voltage (Di, col. 3, lines 56-62).
Regarding claim 14, Keskin, Rezaei, and Di together disclose the limitations
of claim 10. Rezaei teaches a polymorphic latch, Di teaches a polymorphic gate, and further through Keskin:
wherein the first latch or the second latch (Fig. 7A: 710a & 710b) comprises a pair of gates (it is known in the art that d-latches have a pair of NAND gates or a pair of NOR gates).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Keskin (US Pub. 20090079483 A1), Rezaei (“Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries”), and Di (US Pat. 11095287 B1) as applied to claim 10 above, and further in view of Cui et al. (“Design of the RRAM-Based Polymorphic Look-Up Table Scheme”; “Cui”).
Regarding claim 15, Keskin, Rezaei, and Di together disclose the limitations
of claim 10. Rezaei teaches a polymorphic latch. Neither Keskin, Rezaei, nor Di discloses:
polymorphic latch comprises at least one lookup table.
However, Cui teaches:
polymorphic latch comprises at least one lookup table (Fig. 1(a) on p.950, left column, shows an RRAM device with a polymorphic Look-Up Table device; see description starting with the header “A. THE GATE CIRCUIT” at the bottom of the right column of p.949).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cui to modified Keskin wherein a polymorphic latch comprises at least one lookup table in order to provide a multi-input LUT based on a RRAM polymorphic gate (Cui, p.949, Abstract).
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Keskin (US Pub. 20090079483 A1) in view of Rezaei (“Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries”), Yap et al. (US Pub. 20230299773 A1; “Yap”), and Di (US Pat. 11095287 B1).
Regarding independent claim 16, Keskin discloses a latch (Fig. 7A: D latch 710a) comprising:
(i) a pair of gates (NOR gates 418a and 420a; [0045] & [0056]) that is configured as two bistable feedback gates ([0031]),
(ii) an inverter (inverter 412a; [0045]), and
(iii) a pair of AND logic gates (AND gates 414a and 416a; [0045]), wherein:
(a) an AND logic gate (414a) of the pair of AND logic gates comprises a clock signal input (clock signal CLK; [0045]) and (1) a data input or (2) an inverted data input (414a receives an inverted version of input data Din),
(b) the inverted data input is provided by the inverter (412a),
(c) an AND logic gate output of the pair of AND logic gates is coupled to a respectively corresponding gate input of a gate of the pair of gates (414a is coupled to 418a), and
(d) the D-latch (710a) is configured to generate a D-latch output (Q output; [0044]) based on a gate output of the gate.
Keskin does not disclose:
a polymorphic latch
at least one lookup table that is configured with a state table, wherein the state table is associated with a D-latch that comprises:
polymorphic gates
However, Rezaei teaches:
a polymorphic latch (p.536)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Rezaei to Keskin wherein there is a polymorphic latch in order to support a hardware obfuscation method using hybrid memristor-CMOS technology (Rezaei, Abstract).
Also, Yap teaches:
at least one lookup table that is configured with a state table, wherein the state table is associated with a D-latch ([0022]: Each CLB 156 may include a number of look up tables (LUTs) and/or logic elements, which can be selectively combined to perform a desired function through the appropriate interconnection of conductors (e.g., by using D-latches 162). In some embodiments, the LUTs in CLBs 156 may be implemented using latches. Examiner asserts that it is known in the art that a lookup table is configured with a state table) that comprises:
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yap to modified Keskin wherein a polymorphic latch comprises at least one lookup table in order to implement a programmable logic device that uses latches as storage elements to improve area efficiency (Yap, [0001] & [0006]).
Also, Di teaches:
polymorphic gates (Fig. 3)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Di to modified Keskin wherein there are polymorphic gates in order to provide an asynchronous polymorphic circuit that provides two separate functionalities controlled by the supply voltage (Di, col. 3, lines 56-62).
Regarding claim 20, Keskin, Rezaei, Yap, and Di together disclose the limitations of claim 16. Di teaches polymorphic gates. Further, through Keskin:
wherein the D-latch output is provided to a feedback input of the polymorphic gate (in Fig. 7A, Keskin teaches two D latches 710a & 710b. Examiner asserts that the output of 710a is provided to the gates of the NOR circuits of 710b, and by substitution per Di, these NOR circuits may be polymorphic gates).
Allowable Subject Matter
Claims 3, 8-9, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824
/HAN YANG/Primary Examiner, Art Unit 2824
8/8/2026
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