Prosecution Insights
Last updated: October 01, 2026
Application No. 19/026,389

MEMORY DEVICES AND METHODS OF FORMING THE SAME

Non-Final OA §102§103§112
Filed
Jan 17, 2025
Priority
May 27, 2020 — continuation of 11/342,380 +2 more
Examiner
LEBOEUF, JEROME LARRY
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
444 granted / 520 resolved
+25.4% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
24 currently pending
Career history
543
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.6%
+6.6% vs TC avg
§102
26.1%
-13.9% vs TC avg
§112
22.0%
-18.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 520 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: -- MEMORY DEVICES IMPLEMENTING WORK FUNCTION LAYERS AND METHODS OF FORMING THE SAME-- Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 2, 3, 9-15, and 18-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim(s) 2 recite(s) the language (emphasis added) “a selector layer disposed between the first barrier layers and the second electrode”, where it is unclear how a layer can be between more than two distinct elements in a layered stack. Claim(s) 9 recite(s) the language (emphasis added) “a selector layer disposed between the first barrier layers and the second work function layer”, where it is unclear how a layer can be between more than two distinct elements in a layered stack. Claim(s) 18 recite(s) the language (emphasis added) “a selector layer between the first work function layers and the third electrode”, where it is unclear how a layer can be between more than two distinct elements in a layered stack. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4 and 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yi, US 20120228575 A1. As to claim 1, Yi discloses a device (see Yi Fig 12), comprising: a memory layer (see Yi Fig 12 Ref 1210) disposed over a first electrode (see Yi Fig 12 Ref 1204); a plurality of first work function layers (see Yi Fig 12 lowest portion of Ref 1212, Ref 1218, and Para [0029]; There is a work function between layers dissimilar band gaps.) disposed over the memory layer; a plurality of first barrier layers (see Yi Fig 12 upper portion of Ref 1212 and lower portion of Ref 1208) disposed over the first work function layers; and a second electrode disposed over the first barrier layers (see Yi Fig 12 Ref 1202). As to claim 4, Yi discloses the device of claim 1, wherein the first barrier layers comprise metal oxide (see Yi Para [0029]). As to claim 7, Yi discloses the device of claim 1, wherein a sidewall of the second electrode is flushed with a sidewall of the first electrode (see Yi Fig 12). As to claim 8, Yi discloses a device (see Yi Fig 12), comprising: a substrate (see Yi Para [0014]; Integrated circuits have substrates, and substrate have their respective components.) having an electric component (see Yi Fig 12 Ref 1210); a first electrode (see Yi Fig 12 Ref 1204) disposed over and electrically connected to the electric component; at least one first work function layer (see Yi Fig 12 lowest portion of Ref 1212 and Para [0029]) disposed over the first electrode; a plurality of first barrier layers (see Yi Fig 12 upper portion of Ref 1212 and Ref 1218) disposed over the first work function layers, wherein the first barrier layers comprise metal oxide (see Yi Para [0029); and at least one second work function layer disposed over the first barrier layers (see Yi Fig 12 upper portion of Ref 1208 and Para [0029]). As to claim 9, Yi discloses the device of claim 8, further comprising a selector layer disposed between the first barrier layers and the second work function layer (see Yi Para [0015]; Memristors are selectors.). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma, US 20210074825 A1. As to claim 1, Sharma discloses a device (see Sharma Fig 3 Ref 102), comprising: a memory layer (see Sharma Fig 3 Ref 120) disposed below a first electrode (see Sharma Fig 2B Ref lower 112-2); a plurality of first work function layers (see Sharma Fig 2B Ref 112-1 and upper 112-2) disposed over the memory layer; a plurality of first barrier layers (see Sharma Fig 2B Refs 115-1 and 115-2) disposed over the first work function layers; and a second electrode disposed over the first barrier layers (see Sharma Fig 2B Ref upper 116-2). Sharma does not explicitly disclose a memory layer disposed over a first electrode However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that electronic devices can be rearranged so that memory elements are above or below selecting elements (see MPEP 2144.04.VI.C). As to claim 2, Sharma discloses the device of claim 1, further comprising a selector layer disposed between the first barrier layers and the second electrode (see Sharma Fig 2B Ref 114). As to claim 3, Sharma discloses the device of claim 2, further comprising at least one second work function layer disposed between the selector layer and the second electrode (see Sharma Fig 2B Ref 116-1 and lower 116-2). As to claim 7, Sharma discloses the device of claim 1, wherein a sidewall of the second electrode is flushed with a sidewall of the first electrode (see Sharma Fig 2B Refs 116-2 and 112-2). Claim(s) 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yi, US 20120228575 A1, in view of Sharma, US 20210074825 A1. As to claim 14, Yi discloses the device of claim 9, further comprising a memristor. Yi does not appear to explicitly disclose a memory layer disposed between the first electrode and the selector layer. Sharma discloses a memory layer disposed between the first electrode and the selector layer (see Sharma Fig 1A Refs 108 and 110). It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a device, as disclosed by Yi, may be implemented in a memory device stack, as disclosed by Sharma. The inventions are well known variants of devices used for accessing electronic components, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Sharma’s attempt to enable low power memory operations (see Sharma Para [0026]). As to claim 15, Yi and Sharma the disclose the device of claim 14, further comprising a second electrode between the memory layer and the selector layer (see Sharma Fig 1A Ref 112). As to claim 16, Yi and Sharma the device of claim 15, further comprising a third electrode layer disposed over the second work function layer (see Yi Fig 12 Ref 1202). As to claim 17, Yi discloses a method of forming a device (see Yi Fig 12), comprising: providing a substrate (see Yi Para [0014]; Integrated circuits have substrates, and substrate have their respective components.) having an electric component (see Yi Fig 12 Ref 1210); forming a second electrode (see Yi Fig 12 Ref 1204) over another layer; forming a plurality of first work function layers (see Yi Fig 12 lowest portion of Ref 1212, upper portion of Ref 1208, and Para [0029]) over the second electrode; forming a plurality of first barrier layers (see Yi Fig 12 upper portion of Ref 1212 and Ref 1218) over the first work function layers; and forming a third electrode over the first work function layers (see Yi Fig 12 Ref 1202). Yi does not seem to explicitly disclose forming a first electrode over the substrate and electrically connected to the electric component; forming a memory layer over the first electrode. Sharma discloses a first electrode (see Sharma Fig 1A Ref 108) over the substrate and electrically connected to the electric component; forming a memory layer (see Sharma Fig 1A Ref 110) over the first electrode. It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a device, as disclosed by Yi, may be implemented in a memory device stack, as disclosed by Sharma. The inventions are well known variants of devices used for accessing electronic components, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Sharma’s attempt to enable low power memory operations (see Sharma Para [0026]). As to claim 18, Yi and Sharma the method of claim 17, further comprising forming a selector layer between the first work function layers and the third electrode (see Yi Para [0015]; Memristors are selectors.). Allowable Subject Matter Claims 5, 6, 10-13, 19, and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not appear to disclose (as recited in claim 5): a work function of one of the first barrier layers increases as the one of the first barrier layers becomes closer to the second electrode. The prior art does not appear to disclose (as recited in claim 10): a work function of one of the first barrier layers increases as the one of the first barrier layers becomes closer to the selector layer. The prior art does not appear to disclose (as recited in claim 11): the at least one first work function layers comprises a plurality of first work function layers, and a work function of one of the first work function layers increases as the one of the first work function layers becomes closer to the selector layer. The prior art does not appear to disclose (as recited in claim 12): a thickness of one of the first work function layers decreases as the one of the first work function layers becomes closer to the selector layer. The prior art does not appear to disclose (as recited in claim 13): a thickness of one of the first barrier layers decreases as the one of the first barrier layers becomes closer to the selector layer. The prior art does not appear to disclose (as recited in claim 19): forming at least one second work function layer between the selector layer and the third electrode. The prior art does not appear to disclose (as recited in claim 20): forming a second barrier layer between the selector layer and the second work function layer. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cheng, US 20210111224 A1 discloses first and second barrier layers. Karpov, US 20200075851 A1 discloses a metal oxide. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEROME LEBOEUF/Primary Examiner, Art Unit 2824 – 08/22/2026
Read full office action

Prosecution Timeline

Jan 17, 2025
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
92%
With Interview (+6.4%)
2y 0m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 520 resolved cases by this examiner. Grant probability derived from career allowance rate.

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