DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asnaashari et al. (US 9,697,874 “Asnaashari”) in view of Yamazaki et al. (US 2016/0247548 “Yamazaki”).
Regarding claim 1, Asnaashari discloses a semiconductor device comprising:
a COMS logic circuit (210; fig. 2); and
a memory device (200; fig. 2) over the COMS logic circuit,
wherein the COMS logic circuit comprises a CPU (CPU; fig. 2) and a bus (260; fig. 2),
wherein the memory device comprises a memory cell (220-250; fig. 2),
wherein the memory cell comprises a first transistor, a second transistor, a third transistor (fig. 3-6), and
wherein data communication between the memory device and the CPU is performed through the bus (column/line(s): 12/36-56).
Asnaashari does not expressly disclose a capacitor, and wherein the first transistor, the second transistor, and the third transistor each comprise a channel formation region including a metal oxide.
Yamazaki discloses a capacitor (any capacitor of memory cell; fig. 1-3, 6-17), and wherein the first transistor, the second transistor, and the third transistor each comprise a channel formation region (432 [0195]) including a metal oxide (first M0 to third Mn transistors may comprise metal oxide 432; fig. 1-3, 6-17 [0192-0195]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Asnaashari is modifiable as taught by Yamazaki for the purpose of allowing a large amount of current flow to increase an on-state of a transistor, suitable for achieving high density circuits such as large-scale integration [0208+ of Yamazaki].
Regarding claim 2, Asnaashari discloses the semiconductor device according to claim 1, wherein the memory device is in a plurality of memory devices, and wherein the plurality of memory devices overlap with the COMS logic circuit (fig. 2).
Regarding claim 3, Asnaashari discloses the semiconductor device according to claim 1, wherein the COMS logic circuit further comprises a first peripheral circuit and a second peripheral circuit (fig. 2).
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asnaashari et al. (US 9,697,874 “Asnaashari”) in view of Yamazaki et al. (US 2016/0247548 “Yamazaki”), and further in view of Ohmaru et al. (US 2014/0204645 “Ohmaru”).
Regarding claim 4, Asnaashari discloses a semiconductor device comprising:
a COMS logic circuit (210; fig. 2); and
a memory device (200; fig. 2) over the COMS logic circuit,
wherein the COMS logic circuit comprises a CPU (CPU; fig. 2) and a bus (260; fig. 2),
wherein the memory device comprises a memory cell (220-250; fig. 2),
wherein the memory cell comprises a retention node, a first transistor, a second transistor, a third transistor (fig. 3-6),
and wherein data communication between the memory device and the CPU is performed through the bus (column/line(s): 12/36-56).
Asnaashari does not expressly disclose wherein the memory device comprises a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a memory cell, and a capacitor,
wherein the first transistor, the second transistor, and the third transistor each comprise a channel formation region including a metal oxide,
wherein a gate of the first transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the retention node,
wherein a gate of the second transistor is electrically connected to the retention node,
wherein a gate of the third transistor is electrically connected to the second wiring,
wherein the second transistor and the third transistor are electrically connected in series between the fourth wiring and the fifth wiring,
wherein a first terminal of the capacitor is electrically connected to the retention node,
wherein a second terminal of the capacitor is electrically connected to the fourth wiring.
Ohmaru discloses wherein the memory device comprises a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a memory cell, and a capacitor (fig. 4),
wherein the first transistor (109; fig. 4), the second transistor (110; fig. 4), each comprise a channel formation region [0163],
wherein a gate of the first transistor (109) is electrically connected to the first wiring (wire for BK input; fig. 4),
wherein one of a source and a drain of the first transistor (109) is electrically connected to the third wiring (wire for storage circuit 320_(m+1) input; fig. 4),
wherein the other of the source and the drain of the first transistor (109) is electrically connected to the retention node (M2; fig. 4),
wherein a gate of the second transistor (110) is electrically connected to the retention node (M2),
wherein a gate of the third transistor (113; fig. 4) is electrically connected to the second wiring (wire for PR input; fig. 4),
the second transistor (110) and the third transistor (113) are electrically connected in series between the fourth wiring (wire for V1 input; fig. 4) and the fifth wiring (M1 wiring; fig. 4),
wherein a first terminal of the capacitor (108; fig. 4) is electrically connected to the retention node (M2),
wherein a second terminal of the capacitor (108) is electrically connected to the fourth wiring (wire for V1 input).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Asnaashari is further modifiable as taught by Ohmaru for the purpose of facilitating data accessing schemes by preventing delays of signals [0019 oh Ohmaru], to benefit, predictably, the commonly understood advantage of having a more efficient and robust operating memory device.
Yamazaki discloses wherein the memory device comprises a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a memory cell, and a capacitor (fig. 1-3, 6-17),
wherein the first transistor, the second transistor, and the third transistor (any of transistors M0-Mn) each comprise a channel formation region (432 [0195]) including a metal oxide (M0 to Mn transistors may comprise metal oxide 432; fig. 1-3, 6-17 [0192-0195]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Asnaashari is further modifiable as taught by Yamazaki for the purpose of allowing a large amount of current flow to increase an on-state of a transistor, suitable for achieving high density circuits such as large-scale integration [0208+ of Yamazaki].
Regarding claim 5, Asnaashari discloses the semiconductor device according to claim 4, wherein the memory device is in a plurality of memory devices, and wherein the plurality of memory devices overlap with the COMS logic circuit (fig. 2).
Regarding claim 6, Asnaashari discloses the semiconductor device according to claim 4, wherein the COMS logic circuit further comprises a first peripheral circuit and a second peripheral circuit (fig. 2).
Allowable Subject Matter
Claim(s) 7-9 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art made of record and not relied upon is considered pertinent to applicant’s disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to independent claim 7 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely wherein a back gate of the first transistor is electrically connected to the sixth wiring, wherein a gate of the second transistor is electrically connected to the retention node, wherein a back gate of the second transistor is electrically connected to the seventh wiring, wherein a gate of the third transistor is electrically connected to the second wiring, wherein a back gate of the third transistor is electrically connected to the eighth wiring.
The allowable claims are supported in at least fig. 1B of the instant application.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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