Prosecution Insights
Last updated: October 01, 2026
Application No. 19/032,453

SENSE AMPLIFIER CIRCUIT, MEMORY CIRCUIT, AND SENSING METHOD THEREOF

Non-Final OA §DOUBLEPATENT
Filed
Jan 21, 2025
Priority
Jun 22, 2022 — divisional of 12/237,009
Examiner
NGUYEN, VIET Q
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1207 granted / 1269 resolved
+35.1% vs TC avg
Minimal +4% lift
Without
With
+3.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
17 currently pending
Career history
1282
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
27.2%
-12.8% vs TC avg
§102
34.3%
-5.7% vs TC avg
§112
23.8%
-16.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1269 resolved cases

Office Action

§DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 1. Claims 1-20 are present for examination. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 2. Claims 1-5, 7, 10-17 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6, 9-11, 13-15 and 17, respectively, of U.S. Patent No. 12,237,009 (same assignee/inventor) as follows: Although the claims at issue are not identical, they are not patentably distinct from each other because the following comparison. Claim 1 and 16 (of this application) obviously recited similar elements and/or similar operation as those of claim 1 and/or claim 17 (of patent ‘009), for a sense amplifier having similar claimed configuration such as, i.e., two input nodes, two output nodes, and similar first and second switches, and a similar method steps using these switches to pre-charge the first and second output nodes, respectively, when the sense amplifier circuit is enabled by a select signal, etc. Thus, both inventions are obviously drawn to a same inventive concept. Claim 2 (application) includes pull-down circuit as that of claim 2 (patent ‘009). Claim 3 (application) includes similar language of claim 3 (patent ‘009). Claim 4 (application) includes similar language as claim 4 (patent ‘009). Claim 5 (application) includes identical language as claim 5 (patent ‘009). Claim 7 (application) includes identical language as claim 6 (patent ‘009). Claim 10 (application) includes identical language as claim 9 (patent ‘009). Claim 11 (application) includes identical language as claim 10 (patent ‘009). Claim 12 (application) includes identical language as claim 11 (patent ‘009). Claim 13 (application) includes identical language as claim 13 (patent ‘009). Claim 14 (application) includes identical language as claim 14 (patent ‘009). Claim 15 (application) includes identical language as claim 15 (patent ‘009). Claim 17 (application) includes identical language as claim 2 (patent ‘009). Claim 19 (application) includes identical language as claim 4 (patent ‘009). Allowable Subject Matter 3. The remaining claims 6, 8-9, 18 & 20 contain other/allowable limitations over the prior arts of record, which are not clearly suggested nor seen elsewhere at this time. 4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VIET Q NGUYEN/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Jan 21, 2025
Application Filed
Aug 18, 2026
Non-Final Rejection mailed — §DOUBLEPATENT (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12743279
An Apparatus and Method of Generating Chip Select Signals
4y 1m to grant Granted Sep 22, 2026
Patent 12745571
SCALABLE SPINTRONIC DEVICES FORMED ON SILICON WAFERS
2y 7m to grant Granted Sep 22, 2026
Patent 12738306
MAGNETIC TUNNEL JUNCTION WITH DUAL REFERENCE LAYERS HAVING PARALLEL MAGNETIZATION DIRECTIONS AND METHODS FOR OPERATING THE SAME
2y 6m to grant Granted Sep 15, 2026
Patent 12727158
READ-ONLY MEMORY DEVICE AND METHOD
3y 0m to grant Granted Sep 01, 2026
Patent 12725667
MEMORY DEVICE AND CONTROL METHOD THEREOF
2y 0m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+3.5%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1269 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month