Notice of Pre-AIA or AIA Status216
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-19 are pending in this action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/21/2025, 06/01/2025, 06/01/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 10-14 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers (US 2004/0,136,273, and further in view of Jhang (US 2020/0,264,949)
As per claim 1:
Chambers discloses:
A system comprising: a memory array comprising non-volatile memory cells arranged
(Chambers, Fig. 7, Non-Volatile Memory 200 with rows and columns)
(Chambers, Fig. 2, Non-Volatile Memory 200)
wherein the array stores a plurality of words, wherein respective words are divided into multiple sub-words and respective non-volatile memory cells in the memory array store digital bits belonging to different sub-words of the plurality of sub-words.
(Chambers [0058]…the data word … is partitioned into a least significant ("LS") subword and a most significant ("MS") subword)
(Chambers, Fig. 9A step 404 shows a method of partition…)
(Chambers [0073] Step 404: Partitioning the N-bit word into a Most Significant (MS) subword and a Least Significant (LS) subword…)
(Chambers, Figs. 7-8 shows a plurality of subword such as …LS Subword V.1 212, LS Subword V1.2, MS Subword v.1 MS subword v.2 )
Chambers does not clearly disclose:
Non-volatile memory is arranged in rows and columns.
Jhang is similar Chambers and the recited claim.
Jhang also discloses a method of dividing a data word into a plurality of sub-data, generating sub ECC for each sub-data word, storing each sub-data word along with sub-ECC for each sub-data word.
(Jhang, Fig. 6 [0036]-[0038] divides the data into a plurality of sub-data.. generates a corresponding sub ECC for each of sub-data)
(Jhang, Fig. 5. Shows first sub-dataword D1 with sub ECC CRC1)
(Jhang, Fig. 5. Shows second sub-dataword D2 with second sub ECC CRC2)
(Jhang, Fig. 5. Shows third sub-dataword D3 with third sub ECC CRC3)
(Jhang, Fig. 5. Shows fourth sub-dataword D4 with fourth sub ECC CRC4)
(Jhang, [0038],… generates a corresponding sub ECC for each of sub-data. … 210 generates sub-error-correcting codes (sub ECCs), which are labeled SECC1 to SECC16, corresponding to the sub-data SD1 to SD16 …sub ECC can be configured to correct an error bit of the sub-data SD, an error bit correcting capability of the sub ECC is, for example, 1 bit, which means that the sub ECC1 can be used to correct 1 error bit in the sub-data SD1)
Jhang discloses:
Non-volatile memory is arranged in rows and columns.
(Jhang, [0026], data storage area 221 of the volatile memory 220 has M columns and N rows, and the check code storage area 222 of the volatile memory 220 has S columns and N rows, where M, S, and N all are positive integers greater than or equal to 2….)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Jhang’s (well-known) method of arranging memory in rows and columns so that the memory can easily be identify.
(Jhang, [0026], data storage area 221 of the volatile memory 220 has M columns and N rows, and the check code storage area 222 of the volatile memory 220 has S columns and N rows, where M, S, and N all are positive integers greater than or equal to 2….)
As per claim 2:
Chambers-Jhang further discloses:
wherein respective non-volatile memory cells of the memory array store a first bit of a first sub-word of the multiple sub-words and a second bit of a second sub-word of multiple sub-words,
(Chambers, Figs. 7-8 shows a plurality of subword such as …LS Subword V.1 212, LS Subword V1.2, MS Subword v.1 MS subword v.2 )
wherein the first sub-word is backed by a first ECC block and
(Chambers, Figs. 7-8 shows the first subword is backed up by ECC m, 212-1 and 216-1 )
the second sub-word is backed by a second ECC block.
(Chambers, Figs. 7-8 shows the second subword is backed up by ECC m, 212-2, 216-2 )
As per claim 3:
Chambers-Jhang further discloses:
wherein the first ECC block can
(Chambers, Figs. 7-8 shows the first subword is backed up by ECC m, 212-1 and 216-1 )
(Chambers, [0068] the ECC is simply a parity bit. In another embodiment, the ECC is a more sophisticated code that is capable of correcting one or more erroneous bits among the N-bit data)
the second ECC block can
(Chambers, Figs. 7-8 shows the second subword is backed up by ECC m, 212-2, 216-2 )
Chambers does not clearly mention 1st and 2nd ECC can correct.
Jhang further discloses:
1st and 2nd ECC can correct.
(Jhang, Fig. 6 [0036]-[0038] divides the data into a plurality of sub-data.. generates a corresponding sub ECC for each of sub-data)
(Jhang, Fig. 5. Shows first sub-dataword D1 with sub ECC CRC1)
(Jhang, Fig. 5. Shows second sub-dataword D2 with second sub ECC CRC2)
(Jhang, Fig. 5. Shows third sub-dataword D3 with third sub ECC CRC3)
(Jhang, Fig. 5. Shows fourth sub-dataword D4 with fourth sub ECC CRC4)
(Jhang, [0038],… generates a corresponding sub ECC for each of sub-data. … 210 generates sub-error-correcting codes (sub ECCs), which are labeled SECC1 to SECC16, corresponding to the sub-data SD1 to SD16 …sub ECC can be configured to correct an error bit of the sub-data SD, an error bit correcting capability of the sub ECC is, for example, 1 bit, which means that the sub ECC1 can be used to correct 1 error bit in the sub-data SD1)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Jhang’s (well-known) of using sub-ECC to correct sub-dataword in order to provide a corrected sub-dataword.
(Jhang, [0038],… generates a corresponding sub ECC for each of sub-data. … 210 generates sub-error-correcting codes (sub ECCs), which are labeled SECC1 to SECC16, corresponding to the sub-data SD1 to SD16 …sub ECC can be configured to correct an error bit of the sub-data SD, an error bit correcting capability of the sub ECC is, for example, 1 bit, which means that the sub ECC1 can be used to correct 1 error bit in the sub-data SD1)
As per claim 4:
Chambers-Jhang further discloses:
wherein respective non-volatile memory cells further store a third bit of a third sub-word of the multiple sub-words and a fourth bit of a fourth sub-word of the multiple sub-words,
(Chambers, Figs. 7-8 shows the third subword is backed up by ECC m, 212-3, 216-3)
(Chambers, Figs. 7-8 shows the fourth subword is backed up by ECC m, 212-4, 216-4)
wherein the third sub-word is backed by a third ECC block and
(Chambers, Figs. 7-8 shows the third subword is backed up by ECC m, 212-3, 216-3)
(Chambers, [0068] the ECC is simply a parity bit. In another embodiment, the ECC is a more sophisticated code that is capable of correcting one or more erroneous bits among the N-bit data)
the fourth sub-word is backed by a fourth ECC block.
(Chambers, Figs. 7-8 shows the fourth subword is backed up by ECC m, 212-4, 216-4)
(Chambers, [0068] the ECC is simply a parity bit. In another embodiment, the ECC is a more sophisticated code that is capable of correcting one or more erroneous bits among the N-bit data)
As per claim 10:
Chambers discloses:
A method comprising:
storing a plurality of words in a memory array comprising non-volatile memory cells
(Chambers, Fig. 7, Non-Volatile Memory 200 with rows and columns)
(Chambers, Fig. 2, Non-Volatile Memory 200)
the plurality of words divided respectively into multiple sub-words and respective ones of the non-volatile memory cells store a plurality of digital bits belonging to different sub-words.
(Chambers [0058]…the data word … is partitioned into a least significant ("LS") subword and a most significant ("MS") subword)
(Chambers, Fig. 9A step 404 shows a method of partition…)
(Chambers [0073] Step 404: Partitioning the N-bit word into a Most Significant (MS) subword and a Least Significant (LS) subword…)
(Chambers, Figs. 7-8 shows a plurality of subword such as …LS Subword V.1 212, LS Subword V1.2, MS Subword v.1 MS subword v.2 )
Chambers does not clearly disclose:
Non-volatile memory is arranged in rows and columns.
Jhang is similar Chambers and the recited claim.
Jhang also discloses a method of dividing a data word into a plurality of sub-data, generating sub ECC for each sub-data word, storing each sub-data word along with sub-ECC for each sub-data word.
(Jhang, Fig. 6 [0036]-[0038] divides the data into a plurality of sub-data.. generates a corresponding sub ECC for each of sub-data)
(Jhang, Fig. 5. Shows first sub-dataword D1 with sub ECC CRC1)
(Jhang, Fig. 5. Shows second sub-dataword D2 with second sub ECC CRC2)
(Jhang, Fig. 5. Shows third sub-dataword D3 with third sub ECC CRC3)
(Jhang, Fig. 5. Shows fourth sub-dataword D4 with fourth sub ECC CRC4)
(Jhang, [0038],… generates a corresponding sub ECC for each of sub-data. … 210 generates sub-error-correcting codes (sub ECCs), which are labeled SECC1 to SECC16, corresponding to the sub-data SD1 to SD16 …sub ECC can be configured to correct an error bit of the sub-data SD, an error bit correcting capability of the sub ECC is, for example, 1 bit, which means that the sub ECC1 can be used to correct 1 error bit in the sub-data SD1)
Jhang discloses:
Non-volatile memory is arranged in rows and columns.
(Jhang, [0026], data storage area 221 of the volatile memory 220 has M columns and N rows, and the check code storage area 222 of the volatile memory 220 has S columns and N rows, where M, S, and N all are positive integers greater than or equal to 2….)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Jhang’s (well-known) method of arranging memory in rows and columns so that the memory can easily be identify.
(Jhang, [0026], data storage area 221 of the volatile memory 220 has M columns and N rows, and the check code storage area 222 of the volatile memory 220 has S columns and N rows, where M, S, and N all are positive integers greater than or equal to 2….)
As per claim 11:
Chambers-Jhang further discloses:
storing ECC data for a first bit of the plurality of digital bits in a first ECC block in the array; and
(Chambers, Figs. 7-8 shows a plurality of subword such as …LS Subword V.1 212, LS Subword V1.2, MS Subword v.1 MS subword v.2 )
(Chambers, Figs. 7-8 shows the first subword is backed up by ECC m, 212-1 and 216-1 )
storing ECC data for a second bit of the plurality of digital bits in a second ECC block in the array.
(Chambers, Figs. 7-8 shows a plurality of subword such as …LS Subword V.1 212, LS Subword V1.2, MS Subword v.1 MS subword v.2 )
(Chambers, Figs. 7-8 shows the second subword is backed up by ECC m, 212-2, 216-2 )
As per claim 12:
Chambers-Jhang further discloses:
(Chambers, Figs. 7-8 shows a plurality of subword such as …LS Subword V.1 212, LS Subword V1.2, MS Subword v.1 MS subword v.2 )
(Chambers, Figs. 7-8 shows the first subword is backed up by ECC m, 212-1 and 216-1 )
(Chambers, Figs. 7-8 shows a plurality of subword such as …LS Subword V.1 212, LS Subword V1.2, MS Subword v.1 MS subword v.2 )
(Chambers, Figs. 7-8 shows the second subword is backed up by ECC m, 212-2, 216-2 )
Chambers does not clearly mention 1st and 2nd ECC can correct.
Jhang further discloses:
1st and 2nd ECC can correct.
(Jhang, Fig. 6 [0036]-[0038] divides the data into a plurality of sub-data.. generates a corresponding sub ECC for each of sub-data)
(Jhang, Fig. 5. Shows first sub-dataword D1 with sub ECC CRC1)
(Jhang, Fig. 5. Shows second sub-dataword D2 with second sub ECC CRC2)
(Jhang, Fig. 5. Shows third sub-dataword D3 with third sub ECC CRC3)
(Jhang, Fig. 5. Shows fourth sub-dataword D4 with fourth sub ECC CRC4)
(Jhang, [0038],… generates a corresponding sub ECC for each of sub-data. … 210 generates sub-error-correcting codes (sub ECCs), which are labeled SECC1 to SECC16, corresponding to the sub-data SD1 to SD16 …sub ECC can be configured to correct an error bit of the sub-data SD, an error bit correcting capability of the sub ECC is, for example, 1 bit, which means that the sub ECC1 can be used to correct 1 error bit in the sub-data SD1)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Jhang’s (well-known) of using sub-ECC to correct sub-dataword in order to provide a corrected sub-dataword.
(Jhang, [0038],… generates a corresponding sub ECC for each of sub-data. … 210 generates sub-error-correcting codes (sub ECCs), which are labeled SECC1 to SECC16, corresponding to the sub-data SD1 to SD16 …sub ECC can be configured to correct an error bit of the sub-data SD, an error bit correcting capability of the sub ECC is, for example, 1 bit, which means that the sub ECC1 can be used to correct 1 error bit in the sub-data SD1)
As per claim 13:
Chambers-Jhang further discloses:
storing ECC data for a third bit of the plurality of digital bits in a third ECC block in the array; and
(Chambers, Figs. 7-8 shows the third subword is backed up by ECC m, 212-3, 216-3)
(Chambers, Figs. 7-8 shows the fourth subword is backed up by ECC m, 212-4, 216-4)
storing ECC data for a fourth bit of the plurality of digital bits in a fourth ECC block in the array.
(Chambers, Figs. 7-8 shows the fourth subword is backed up by ECC m, 212-4, 216-4)
(Chambers, [0068] the ECC is simply a parity bit. In another embodiment, the ECC is a more sophisticated code that is capable of correcting one or more erroneous bits among the N-bit data)
As per claim 14:
Chambers-Jhang further discloses:
(Chambers, Figs. 7-8 shows the fourth subword is backed up by ECC m, 212-4, 216-4)
(Chambers, [0068] the ECC is simply a parity bit. In another embodiment, the ECC is a more sophisticated code that is capable of correcting one or more erroneous bits among the N-bit data)
Chambers does not clearly mention ECC can correct.
Jhang further discloses:
ECC can correct
(Jhang, Fig. 6 [0036]-[0038] divides the data into a plurality of sub-data.. generates a corresponding sub ECC for each of sub-data)
(Jhang, Fig. 5. Shows first sub-dataword D1 with sub ECC CRC1)
(Jhang, Fig. 5. Shows second sub-dataword D2 with second sub ECC CRC2)
(Jhang, Fig. 5. Shows third sub-dataword D3 with third sub ECC CRC3)
(Jhang, Fig. 5. Shows fourth sub-dataword D4 with fourth sub ECC CRC4)
(Jhang, [0038],… generates a corresponding sub ECC for each of sub-data. … 210 generates sub-error-correcting codes (sub ECCs), which are labeled SECC1 to SECC16, corresponding to the sub-data SD1 to SD16 …sub ECC can be configured to correct an error bit of the sub-data SD, an error bit correcting capability of the sub ECC is, for example, 1 bit, which means that the sub ECC1 can be used to correct 1 error bit in the sub-data SD1)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Jhang’s (well-known) of using sub-ECC to correct sub-dataword in order to provide a corrected sub-dataword.
(Jhang, [0038],… generates a corresponding sub ECC for each of sub-data. … 210 generates sub-error-correcting codes (sub ECCs), which are labeled SECC1 to SECC16, corresponding to the sub-data SD1 to SD16 …sub ECC can be configured to correct an error bit of the sub-data SD, an error bit correcting capability of the sub ECC is, for example, 1 bit, which means that the sub ECC1 can be used to correct 1 error bit in the sub-data SD1)
Claim(s) 5 and 15 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers (US 2004/0,136,273, and further in view of Jhang (US 2020/0,264,949), in view of Patapoutian et al (US 2012/0,079,355)
As per claim 5:
As per claim 15:
Chambers-Jhang further discloses:
wherein respective non-volatile memory cell are … multi-level memory cell.
(Chambers, Fig. 7, Non-Volatile Memory 200 with rows and columns)
(Chambers, Fig. 2, Non-Volatile Memory 200)
Chambers-Jhang does not disclose:
wherein respective non-volatile memory cell are digital multi-level memory cells.
Patapoutian discloses:
wherein respective non-volatile memory cell are digital multi-level memory cells.
(Patapoutian, [0035], memory 105 may comprise single level cells (SLC) or multilevel cells (MLC)….s an MLC memory is capable of storing digital symbols of two, three, or more bits per memory cell)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Pataputian’s digital multi-level memory unit in order to allow Chambers-Jhang to select digital multi-level memory as one of the memory for the system.
(Patapoutian, [0035], memory 105 may comprise single level cells (SLC) or multilevel cells (MLC)….s an MLC memory is capable of storing digital symbols of two, three, or more bits per memory cell)
Claim(s) 6 and 16 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers (US 2004/0,136,273, and further in view of Jhang (US 2020/0,264,949), in view of Feder et al (US 2011/0,289,286)
As per claim 6:
As per claim 16:
Chambers-Jhang further discloses:
wherein respective non-volatile memory cell are … multi-level memory cell.
(Chambers, Fig. 7, Non-Volatile Memory 200 with rows and columns)
(Chambers, Fig. 2, Non-Volatile Memory 200)
Chambers-Jhang does not disclose:
wherein respective non-volatile memory cell are analog multi-level memory cells.
Feder discloses:
wherein respective non-volatile memory cell are
(Feder, [0030] memory unit 100 is an analog multi-level memory unit)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Federer’s analog multi-level memory unit in order to allow Chambers-Jhang to select analog multi-level memory as one of the memory for the system.
(Feder, [0030] memory unit 100 is an analog multi-level memory unit)
Claim(s) 7 and 17 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers (US 2004/0,136,273, and further in view of Jhang (US 2020/0,264,949), in view of Okazaki et al (US 2023/0,385,619)
As per claim 7:
As per claim 17:
Chambers-Jhang further discloses:
wherein the array is a
(Chambers, Fig. 7, Non-Volatile Memory 200 with rows and columns)
(Chambers, Fig. 2, Non-Volatile Memory 200)
Chambers-Jhang does not disclose:
wherein the array is a vector-by-matrix multiplication array in a neural network.
Okazaki discloses:
wherein the array is a vector-by-matrix multiplication array in a neural network.
(Okazaki, [0032]… implemented as vector-matrix multiplication on large NVM-based arrays… The crossbar array of synaptic cells with NVM (conductance) and transistor pairs is ideally suited for the MAC operations at the heart of (deep neural networks) DNN learning)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Okazaki’s vector-by-matrix multiplication array memory in order to allow Chambers-Jhang to apply its application in neural network learning.
(Okazaki, [0032]… implemented as vector-matrix multiplication on large NVM-based arrays… The crossbar array of synaptic cells with NVM (conductance) and transistor pairs is ideally suited for the MAC operations at the heart of (deep neural networks) DNN learning)
Claim(s) 8 and 18 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers (US 2004/0,136,273, and further in view of Jhang (US 2020/0,264,949), in view of Wu et al. (US 2017/0,170,188)
As per claim 8:
As per claim 18:
Chambers-Jhang further discloses:
wherein respective non-volatile memory cell are
(Chambers, Fig. 7, Non-Volatile Memory 200 with rows and columns)
(Chambers, Fig. 2, Non-Volatile Memory 200)
Chambers-Jhang does not disclose:
wherein respective non-volatile memory cell are split-gate flash memory cells
Wu discloses:
wherein respective non-volatile memory cell are split-gate flash memory cells
(Wu, [0023], NVM device 118 comprises a plurality of split gate flash memory cells which respectively include a select gate 310 and a control gate 314 separated by a charge trapping layer 124)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Wu’s split gate flash memory on order to allow Chambers-Jhang to select one of the type of NVM memory.
(Wu, [0023], NVM device 118 comprises a plurality of split gate flash memory cells which respectively include a select gate 310 and a control gate 314 separated by a charge trapping layer 124)
Claim(s) 8 and 18 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers (US 2004/0,136,273, and further in view of Jhang (US 2020/0,264,949), in view of Shimizu (US 2022/0,352,189)
As per claim 9:
As per claim 19
Chambers-Jhang further discloses:
wherein respective non-volatile memory cell are
(Chambers, Fig. 7, Non-Volatile Memory 200 with rows and columns)
(Chambers, Fig. 2, Non-Volatile Memory 200)
Chambers-Jhang does not disclose:
wherein respective non-volatile memory cell are stacked- gate flash memory cell.
Shimizu discloses:
wherein respective non-volatile memory cell are stacked- gate flash memory cell.
(Shimizu, [0125], non-volatile semiconductor memory MC is, for example, a stacked gate flash memory)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Shimizu’s stacked gate flash memory on order to allow Chambers-Jhang to select one of the type of NVM memory.
(Shimizu, [0125], non-volatile semiconductor memory MC is, for example, a stacked gate flash memory)
Conclusion
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/Thien Nguyen/ Primary Examiner, Art Unit 2111
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