DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 01/27/2025, 12/19/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings submitted on 01/27/2025. These drawings are reviewed and accepted by the examiner.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it uses the phrase “disclosure” in page 1, line 1, which is implied. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12-13 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Takagi et al (US 8,179,714 B2 hereinafter “Takagi”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 12, Takagi, for example in Figs. 1-18, discloses a memory circuit (e.g., memory 200; in Fig. 5 related in Figs. 1-4, 6-18), comprising: a memory cell (e.g., memory cell 300; in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-18) coupled to a resistor in series (e.g., variable resistance element 309; in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-18) with a transistor (e.g., transistor 317; in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-18); and a programming circuit (e.g., Write circuit 206; in Fig. 5 related in Figs. 1-4, 6-18) configured to program the memory cell according to a program voltage (e.g., a select word line WL0 at 2.2V or VDD; in Figs. 7, 9, 14 related in Figs. 1-6, 8, 10-13, 15-18), wherein in response to receiving the program voltage at a word line coupled to the transistor (e.g., WL0; in Figs. 7, 9, 14 related in Figs. 1-6, 8, 10-13, 15-18), a bulk port of the memory cell (e.g., BB0; in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-18) is biased at a first bulk voltage (e.g., VB or 0.3V; in Figs. 7, 9, 14 related in Figs. 1-6, 8, 10-13, 15-18).
Regarding claim 13, Takagi, for example in Figs. 1-18, discloses further comprising: a sensing circuit (e.g., Sense amplifier 204; in Fig. 5 related in Figs. 1-4, 6-18) coupled to the memory cell via a read access transistor (e.g., transistor N11; in Fig. 5 related in Figs. 1-4, 6-18), the sensing circuit configured to sense the memory cell in response to a read enable voltage (e.g., Vread; in Fig. 7 related in Figs. 1-6, 8-18).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Takagi et al (US 8,179,714 B2 hereinafter “Takagi”) in view of Pikhay et al (US 7,400,538 B2 hereinafter “Pikhay”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 15, Takagi, for example in Figs. 1-18, discloses the claimed invention as discussed above. However, Takagi is silent with regard to the memory cell comprises an electronic fuse (eFuse).
In the same field of endeavor, Pikhay, for example in Figs. 1-14, discloses the memory cell (e.g., NROM; in Fig. 14 related in Figs. 1-13) comprises an electric fuse (eFuse) (e.g., Protection fuse 202; in Fig. 14 related in Figs. 1-13).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Takagi such as non-volatile storage device (see for example in Figs. 1-18 of Takagi) by incorporating the teaching of Pikhay such as NROM memory device (see for example in Figs. 1-14 of Pikhay), for the purpose of controlling the local charge trapping arrangement facilitates "two bit operation"--i.e., programming the cell in different directions to store two bits of information in the single cell. (see Pikhay disclosed).
Regarding claim 16, the above Takagi/Pikhay, combination discloses wherein the transistor of the memory cell is one of a deep n-well (DNW) transistor or a bulk transistor (e.g., Deep N-well or P+; in Figs. 12 related in Figs. 1-11, 13-14 of Pikhay and also see in Fis. 1-18 of Takagi, as discussed above).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Takagi et al (US 8,179,714 B2 hereinafter “Takagi”) in view of Yoon et al (US 10,437,749 B2 hereinafter “Yoon”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 17, Takagi, for example in Figs. 1-18, discloses the claimed invention as discussed above. However, Takagi is silent with regard to the programming circuit comprises a write access transistor configured to receive a write enable voltage.
In the same field of endeavor, Yoon, for example in Figs. 1-8, discloses the programming circuit (e.g., 130; in Fig. 1 related in Figs. 2-8) comprises a write access transistor (e.g., 150; in Fig. 1 related in Figs. 2-8) configured to receive a write enable voltage (e.g., -VPGM/2; in Fig. 1 related in Figs. 2-8).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Takagi such as non-volatile storage device (see for example in Figs. 1-18 of Takagi) by incorporating the teaching of Yon such as electronic device (see for example in Figs. 1-8 of Yoon), for the purpose of controlling the first selection circuit may couple the write circuit to a first line based on a first selection signal, and may allow cell current corresponding to the write current to flow to the first line (Yoon, see abstract).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, the prior arts of record fail to teach or suggest a memory circuit as recited in claim 14, and particularly, wherein in response to receiving a read voltage at the word line coupled to the transistor, the bulk port of the memory cell is biased at a second bulk voltage, a first voltage level of the first bulk voltage being less than a second voltage level of the second bulk voltage.
Claims 1-11, 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance: The prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations. Takagi et al (US 8,179,714 B2 hereinafter “Takagi”), Gendrier et al (US 7,333,362 B2 hereinafter “Gendrier”), Lee et al (US 9,196,361 B2 hereinafter “Lee”) discloses a memory cell programming state by biasing a voltage at 5V or 11V at substrate; a memory cell read state by biasing a 3.3V at substrate. However, Takagi, Gendrier, Lee, taken individually or in combination, do not teach the claimed invention having the following limitations, in combination with the remaining claimed limitations:
Per claim 1, there is no teaching, suggestion, or motivation for combination in the prior art to a method comprising: during a first time period: receiving, through a word line coupled to a memory cell, a program voltage; and receiving, at a bulk port of the memory cell, a first bulk voltage; and during a second time period: receiving, through the word line, a read voltage; and receiving, at the bulk port, a second bulk voltage, wherein a first voltage level of the first bulk voltage is less than a second voltage level of the second bulk voltage.
Per claim 18, there is no teaching, suggestion, or motivation for combination in the prior art to a method, comprising: providing, by a programming circuit, a programming voltage to a plurality of memory cells; receiving, at a first memory cell of the plurality of memory cells, a write enable voltage and a first bulk voltage; and receiving, at a second memory cell of the plurality of memory cells, a write disable voltage and a second bulk voltage, wherein a second voltage level of the second bulk voltage is less than a first voltage level of the first bulk voltage.
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 09/19/2026
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