DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 13 is objected to because of the following informalities:
The article “an” before “first unselected voltage” in claim 13, line 2 should be “a”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-9 and 13-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3 and 11-16 of U.S. Patent No. 11,776,595 Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 3-6 and 9 are anticipated by claims 1, 3, 11, 13, 14 of the patent and claims 2, 7, 8 and 13-20 would have been obvious over claims 1, 12, 13, 15 and 16.
Regarding claim 1, claim 1 of the patent recites a memory device, comprising:
a memory controller coupled to a memory cell, the memory controller configured to (claim 1, lines 6-7):
apply a first write voltage to a bit line of the memory cell during a memory operation involving the memory cell (claim 1, lines 8-11); and
apply a second write voltage to a gate electrode of the memory cell during the memory operation (claim 1, lines 12-14),
wherein the second write voltage is between the first write voltage and a third write voltage applied to a source line of the memory cell (claim 1, lines 15-18).
Regarding claim 19, it would have been obvious to one having ordinary skill in the art to recognize that the memory system of claim 1 of the patent is used to perform the method of claim 19.
Regarding claims 2, 7, 8, 13, 15 and 20, it would have been obvious to one having ordinary skill in the art to recognize that the memory device of claim 1 and the memory system of claim 1 are identical in structure; therefore, the differences between claims 2, 7, 8, 13, 15 and 20 and claim 1 of the patent are only functional limitations.
Rgearding claim 3, claim 1 of the patent recites the memory device of claim 1, wherein the memory controller is further configured to apply the third write voltage to the source line coupled to the memory cell during the memory operation (claim 1, lines 15-16).
Regarding 4, claim 1 of the patent recites the memory device of claim 1, wherein the gate electrode of the memory cell is coupled to a word line, and wherein the memory controller is configured to apply the second write voltage to the word line (claim 1, lines 12-14).
Regarding claim 5, claim 11 of the patent recites the memory device of claim 1, wherein the memory cell comprises one or more of an e-fuse element or a programmable resistor.
Regarding 6, claim 3 of the patent recites the memory device of claim 1, wherein the memory controller is to:
apply the second write voltage to a second bit line coupled to a second memory cell during the memory operation, the second memory cell coupled to the source line, and
apply the second write voltage to a second word line coupled to a second gate electrode of a second select transistor of the second memory cell during the memory operation.
Regarding claim 9, claim 13 or claim 14 of the patent recites the memory device of claim 1, wherein the memory cell comprises one of a magnetic tunnel junction (MTJ) cell or a metal-insulator-metal (MIM) capacitor).
Claims 10 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,776,595 in view of Liu et al. (US 2017/0345496, hereinafter “Liu”).
Claim 10 differs from claim 1 in reciting that the memory cell comprises a P-type select transistor. However, Liu discloses the use of a p-type transistor for selecting a 1T1R bit cell (Fig. 4 and paragraph [0049], lines 1-2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a p-type transistor to select a memory cell in a memory device.
Regarding claim 11, Liu (Fig. 4) shows the memory device of claim 10, wherein a word line (WL) coupled to a gate of the P-type select transistor extends in parallel with the bit line (BL) along a first direction.
Regarding claims 14-16 and 18, claims 15 and 16 of the patent recite a memory system:
a memory array including:
a first memory cell;
a second memory cell;
a first bit line coupled to the first memory cell and the second memory cell (claim 16, lines 5-6); and
a first word line coupled to the first memory cell and the second memory cell (claim 15, lines 5-6), wherein the first memory cell is coupled to a first source line and the second memory cell is coupled to a second source line (claim 15; lines 7-9) and
a memory controller to:
apply a first voltage (third write voltage) to the first bit line during a first time period to write data to the first memory cell (claim 16, lines 9-10); and
apply a second voltage to a gate electrode of the first memory cell during the first time period (claim 16, lines 11-12),
It would have been obvious to one having ordinary skill in the art to recognize that the memory system of claim 14 and the memory system of claim 15 and 16 of the patent are identical in structure; therefore, differences between claims 14-16 and 18 of the instant application and claims 15 and 16 of the patent are only functional limitations.
Regarding claim 17, it would have been obvious to one having ordinary skill in the art to recognize that the first memory cell or the second memory cell is the memory cell of the memory system of claims 12 or 13, wherein each comprises one or more of a magnetic tunnel junction (MTJ) cell or a metal-insulator- metal (MIM) capacitor).
Claims 1-9 and 13-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 11, 9, 4, 5, 6, 10, 13, 15, of U.S. Patent No. 12,217,822. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 3-9, 14, 16, 18 and 19 are anticipated by claims 1, 2, 4-6, 9, 11, 13, 15 and 18 of the patent and claims 2, 13, 15, 17 and 20 would have been obvious over claims 1, 9 and 10 of the patent.
Regarding claim 1, claim 1 of the patent recites a memory device, comprising:
a memory controller coupled to a memory cell, the memory controller configured to:
apply a first write voltage to a bit line of the memory cell during a memory operation involving the memory cell (claim 1, lines 6-7); and
apply a second write voltage to a gate electrode of the memory cell during the memory operation (claim 1, lines 8-9),
wherein the second write voltage is between the first write voltage and a third write voltage applied to a source line of the memory cell (claim 1, lines 12-15).
Regarding claims 2, 13, 15 and 20, it would have been obvious to one having ordinary skill in the art to recognize that the memory device of claim 1 and the memory system of claim 1 are identical in structure; therefore, the differences between claims 2, 13, 15 and 20 and claim 1 of the patent are only functional limitations.
Regarding claim 3, claim 2 of the patent recites the memory device of claim 1, wherein the memory controller is further configured to apply the third write voltage to the source line coupled to the memory cell during the memory operation.
Regarding claim 4, claim 11 of the patent recites the memory device of claim 1, wherein the gate electrode of the memory cell is coupled to a word line, and wherein the memory controller is configured to apply the second write voltage to the word line.
Regarding claim 5, claim 9 of the patent recites the memory device of claim 1, wherein the memory cell comprises one or more of an e-fuse element or a programmable resistor (a magnetic tunnel junction is a programmable resistor).
Regarding claim 6, claim 4 recites the memory device of claim 1, wherein the memory controller is to:
apply the second write voltage to a second bit line coupled to a second memory cell during the memory operation, the second memory cell coupled to the source line, and
apply the second write voltage to a second word line coupled to a second gate electrode of a second select transistor of the second memory cell during the memory operation.
Regarding claim 7, claim 5 of the patent recites the memory device of claim 1, wherein the memory controller is to:
apply a first read voltage to the bit line coupled to the memory cell during a second memory operation; and
apply a second read voltage to the source line coupled to the memory cell during the second memory operation.
Regarding claim 8, claim 6 of the patent the memory device of claim 7, wherein the memory controller is to: apply a third read voltage to the gate electrode of the memory cell during the second memory operation, the first read voltage between the second read voltage and the third read voltage.
Regarding claim 9, claim 9 or claim 10 of the patent recites the memory device of claim 1, wherein the memory cell comprises one of a magnetic tunnel junction (MTJ) cell or a metal-insulator-metal (MIM) capacitor).
Claims 10 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,217,822 in view of Liu et al. (US 2017/0345496, hereinafter “Liu”).
Claim 10 differs from claim 1 in reciting that the memory cell comprises a P-type select transistor. However, Liu discloses the use of a p-type transistor for selecting a 1T1R bit cell (Fig. 4 and paragraph [0049], lines 1-2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a p-type transistor to select a memory cell in a memory device.
Regarding claim 11, Liu (Fig. 4) shows the memory device of claim 10, wherein a word line (WL) coupled to a gate of the P-type select transistor extends in parallel with the bit line (BL) along a first direction.
Regarding claim 14, claim 13 of the patent recites a memory system:
a memory array including:
a first memory cell;
a second memory cell;
a first bit line coupled to the first memory cell and the second memory cell; and
a first word line coupled to the first memory cell and the second memory cell, wherein the first memory cell is coupled to a first source line and the second memory cell is coupled to a second source line; and
a memory controller to:
apply a first voltage to the first bit line during a first time period to write data to the first memory cell; and
apply a second voltage to a gate electrode of the first memory cell during the first time period,
wherein the second voltage is between the first voltage and a third voltage applied to the first source line of the first memory cell.
Regarding claim 16, claim 15 of the patent recites the memory system of claim 14, wherein the memory controller is further configured to:
apply a fourth voltage (a first read voltage) to the first bit line coupled to the first memory cell during a second time period; and
apply a fifth voltage (a second read voltage) to the first source line coupled to the first memory cell during the second time period.
Regarding claim 17, it would have been obvious to one having ordinary skill in the art to recognize that the first memory cell or the second memory cell is the memory cell of the memory system of claims 9 or 10, wherein each comprises one or more of a magnetic tunnel junction (MTJ) cell or a metal-insulator- metal (MIM) capacitor).
Regarding claim 18, claim 1 recites the memory system of claim 14, wherein the memory controller is further configured to apply the third voltage to the second source line during a second time period.
Regarding claim 19, claim 18 of the patent recites a method, comprising:
applying, by a memory controller, a first write voltage to a bit line of a memory cell during a memory operation involving the memory cell; and
applying, by the memory controller, a second write voltage to a gate electrode of the memory cell during the memory operation (it is inherent that the word line is connected to the gate electrode of the select transistor),
wherein the second write voltage is between the first write voltage and a third write voltage applied to a source line of the memory cell.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2009/0067229 cited in the IDS filed on 01/27/2025, hereinafter “Kang”).
Regarding claim 1, Kang (Fig. 33a) discloses a memory device, comprising:
a memory controller (Fig. 40, 160) coupled to a memory cell, the memory controller configured to:
apply a first write voltage (VPP) to a bit line of the memory cell during a memory operation involving the memory cell, and
apply a second write voltage (paragraph [0284], line 2, power voltage) to a gate electrode of the memory cell during the memory operation,
wherein the second write voltage is between the first write voltage and a third write voltage (GND) applied to a source line of the memory cell.
It is inherent that the pumping VPP is greater than the power voltage.
Rgearding claim 3, Kang discloses the memory device of claim 1, wherein the memory controller is further configured to apply the third write voltage (Fig. 33a, GND) to the source line coupled to the memory cell during the memory operation.
Regarding 4, Kang (Fig. 33a) shows the memory device of claim 1, wherein the gate electrode of the memory cell is coupled to a word line, and wherein the memory controller is configured to apply the second write voltage to the word line.
Regarding claim 5, Kang (Fig. 33a) discloses the memory device of claim 1, wherein the memory cell comprises one or more of an e-fuse element or a programmable resistor (PCR).
Regarding claim 6, Kang (Fig. 32) discloses the memory device of claim 1, wherein the memory controller is to:
apply the second write voltage (an unselected voltage) to a second bit line coupled to a second memory cell during the memory operation, the second memory cell coupled to the source line (GND line), and
apply the second write voltage (an unselected voltage) to a second word line coupled to a second gate electrode of a second select transistor of the second memory cell during the memory operation.
Regarding claim 7, Kang (Fig. 34) discloses the memory device of claim 1, wherein the memory controller is to:
apply a first read voltage (Vread) to the bit line coupled to the memory cell during a second memory operation; and
apply a second read voltage (GND) to the source line coupled to the memory cell during the second memory operation.
Regarding claim 8, Kang (Fig. 34) shows the memory device of claim 7, wherein the memory controller is to:
apply a third read voltage (paragraph [0289], power voltage or pumping voltage) to the gate electrode of the memory cell during the second memory operation, the first read voltage between the second read voltage and the third read voltage (Fig. 34 shows Vread is lower than VDD or VPP applied to WL).
Regarding claim 9, Kang discloses the memory device of claim 1, wherein the memory cell comprises one of a magnetic tunnel junction (MTJ) cell (paragraph [0278]) or a metal-insulator-metal (MIM) capacitor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over kang et al. in view of Liu et al. (US 2017/0345496, hereinafter “Liu”).
Claim 10 differs from Kang in reciting that the memory cell comprises a P-type select transistor. However, Liu discloses the use of a p-type transistor for selecting a 1T1R bit cell (Fig. 4 and paragraph [0049], lines 1-2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a p-type transistor to select a memory cell in a memory device.
Regarding claim 11, Liu (Fig. 4) shows the memory device of claim 10, wherein a word line (WL) coupled to a gate of the P-type select transistor extends in parallel with the bit line (BL) along a first direction.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 1, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the source line extends perpendicular to the word line along a second direction.” in combination with the other limitations thereof as is recited in the claim.
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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