DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the initial filing of 1/29/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Der Schaar (US patent publication 20130059240) in view of Adel (US patent publication 20030021467).
Regarding claim 1, Van Der Schaar teaches a method for semiconductor metrology, comprising:
depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer (paragraph 10 describes using multiple layers);
patterning the first and second film layers (paragraph 10) to define:
a first overlay target disposed in a first location on the semiconductor substrate and comprising a first target feature formed in the first film layer and a second target feature formed in the second film layer in a position adjacent to the first target feature (FIG. 4 shows an example of a small overlay target with gratings 32-35. FIG. 9 shows examples of locations where small targets 74 may be located. Paragraph 65 points out that the gratings could be disposed on two different layers for use in measuring overlay); and
a second overlay target disposed in a second location on the semiconductor substrate and comprising a first part, which is identical to the first overlay target (FIG. 9, small target 72b, located adjacent to a large target 72a), and a second part, which is disposed adjacent to the first part (FIG. 9, large target 72a, disposed adjacent to small target 72b);
capturing a first image, using an imaging assembly, of the second overlay target (FIG. 7 shows several ways to image a large target 72a);
processing the first image to compute a target calibration function based on both the first and second parts of the second overlay target (FIG. 10, straight line 86, along with the offset 90);
capturing a second image, using the imaging assembly, of the first overlay target (FIG. 5 shows some images of small targets); and
processing the second image while applying the target calibration function to estimate an overlay error between patterning of the first and second film layers at the first location (FIG. 10 shows applying the details from curve 88, measured using small targets 74 graphed at points 84, applied to the calibration function (straight line 86 and offset 90) to calculate exact overlays of the small targets 74).
The second overlay target taught by Van Der Schaar comprise a larger target 72a and a small target 72b, similar to small targets 74 (see FIG. 9) rather than a pair of targets that would collectively have rotational symmetry of 180° around a normal to the semiconductor substrate.
In the same field of endeavor of overlay marks, Adel does teach overlay targets such that the second overlay target has rotational symmetry of 180° around a normal to the semiconductor substrate (FIG. 15 shows a large overlay mark that has symmetry of 180° around a normal to the semiconductor substrate and can be divided into smaller targets, such as working groups 244A-B and 224C-D (analogous to the small targets of Van Der Schaar. Note the similarity of each individual working group 244A-D with the marks shown in FIG. 4 and 6 of Van Der Schaar.).) . Using more than four marks in a symmetric setup (see paragraph 70) allows for a more accurate measurement of overlay (paragraph 65 of Van Der Schaar, last sentence).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the overlay measurement method of Van Der Schaar by replacing the large/small pairs of marks in the scribe lines with symmetrical composite marks like those of Adel and partial versions of those marks, predictably retaining the benefit Van Der Schaar enjoys of saving space in the area of each die with smaller marks combined with the increased accuracy of larger marks in the scribe lines.
Regarding claim 2, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 1 (as described above).
Van Der Schaar teaches different sizes of first and second parts of the second overlay target, so does not teach that the second part of the second overlay target comprises a rotated copy of the first part.
In the same field of endeavor of overlay marks, Adel does teach that the second part of the second overlay target comprises a rotated copy of the first part (FIG. 15, working groups 244C-D are a rotated copy of working groups 224A-B). By making one half of the mark a rotated copy of the other half, Adel is able to use the symmetry to calculate overlay error (paragraph 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the overlay measurement method of Van Der Schaar as modified by Adel, by having one part of the combined mark be a rotated copy of the other, with predicable results and a reasonable expectation of success.
Regarding claim 3, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 1 (as described above).
Van Der Schaar further teaches that the first overlay target is one of a plurality of first overlay targets, each comprising the first and second target features, disposed at different, respective locations on the semiconductor substrate (FIG. 9 shows many copies of small target 74 spread across die D), and
wherein processing the second image comprises applying the target calibration function to each of the first overlay targets (FIG. 10 shows multiple points 84 measured based on the small targets 74).
Regarding claim 4, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 1 (as described above).
Van Der Schaar further teaches that processing the first image comprises:
using both the first and second parts of the second overlay target in the first image to estimate a first overlay error between the patterning of the first and second film layers (FIG. 10, offset 90, which is based on both adjacent parts of the marks 72 found in and adjacent to the scribe lines as shown in FIG. 9);
using only the second part of the second overlay target to estimate a second overlay error between the patterning of the first and second film layers (FIG. 10, points 82a are based only on the large targets 72a are used to make line 86); and
computing the target calibration function responsively to a difference between the first and the second overlay errors (paragraph 78, the combination of gap 90 and straight line 86 is used to combine the fine details measured by alignment marks 74 in the interior of die D with the courser trends measured in the scribe lines).
While the large marks 72a used by Van Der Schaar to produce points 82a more closely correspond to the second part of the second overlay target of claim 1 than to the first, the combination of the teachings of Van Der Schaar with those of Adel described hereinabove erases the difference (in the combination, the first part is symmetric with the second part and provides greater accuracy (and demands more space) due to including both halves).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the overlay measurement method of Van Der Schaar as modified by Adel, by having the first part of targets 72, rather than the second part, be used to measure points 82a, with predictable results and a reasonable expectation of success.
Regarding claim 5, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 4 (as described above).
Van Der Schaar further teaches that using both
the first and second parts comprises estimating the first overlay error by finding a displacement between respective first centers of symmetry of the first target features and the second target features in both the first and second parts of the second overlay target (paragraph 65 describes features on the two layers to produce a measurement of an offset. FIG. 10 shows that measuring overlay errors is done for each of the two marks 72 in each pair), and
wherein using only the first part comprises estimating the second overlay error by finding a displacement between respective second centers of symmetry of the first target features and the second target features in only the first part of the second overlay target (FIG. 10, points 82a are measured in this way).
Regarding claim 6, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 1 (as described above).
Van Der Schaar further teaches that the first image is captured in a first orientation of the semiconductor substrate, and wherein the method comprises capturing a third image of the second overlay target in a second orientation of the semiconductor substrate, which is rotated by 180° about the normal to the semiconductor substrate relative to the first orientation (paragraph 73 discusses rotating the substrate 180 degrees between measurements), and
wherein processing the first image comprises processing both the first and third images to estimate respective first and second overlay errors in the first and second orientations, and computing the target calibration function based on the first and second overlay errors (paragraph 73 discusses rotating the substrate 180 degrees between measurements).
Regarding claim 7, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 1 (as described above).
Van Der Schaar further teaches that the semiconductor substrate comprises dies (FIG. 9, dice D) separated by scribe lines (FIG. 9, scribe lines SL), and wherein the first overlay target is disposed in a device area of a die (FIG. 9, small targets 74) and the second overlay target is disposed in one of the scribe lines (FIG. 9, large and small targets 72, taken as pairs).
Regarding claim 8, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 1 (as described above).
Van Der Schaar further teaches that the first target feature comprises a first linear grating oriented along a first direction in the first film layer, and the second target feature comprises a second linear grating oriented in the first direction in the second film layer (paragraph 65, which describes how each grating 33 and35 is a composite between features on different layers. Note that FIG. 15 of Adel also has a such pairs of gratings in the X direction.).
Regarding claim 9, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 8 (as described above).
Van Der Schaar further teaches that the first target feature further comprises a third linear grating oriented along a second direction, which is not parallel with the first direction, in the first film layer, and the second target feature comprises a fourth linear grating oriented in the second direction in the second film layer (paragraph 65, which describes how each grating 32 and 34 is a composite between features on different layers. Note that FIG. 15 of Adel also has a such pairs of gratings in the Y direction.).
Regarding claim 10, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 1 (as described above).
Van Der Schaar further teaches measuring an angular misalignment of the semiconductor substrate, wherein applying the target calibration function comprises correcting for the angular misalignment in estimating the overlay error (paragraph 80 lists rotations among the parameters that can be calculated as part of the lower order calibration).
Regarding claim 11, Van Der Schaar, as modified by Adel, teaches or renders obvious the method according to claim 10 (as described above).
Van Der Schaar further teaches that the first overlay target is one of a plurality of the first overlay targets disposed at different, respective locations on the semiconductor substrate (FIG. 9, small targets 74), and wherein measuring the angular misalignment comprises estimating and compensating for a local angular misalignment at each of the different locations (paragraph 80 points out that the small targets 74 are used to measure more local perturbations on the parameters estimated from the marks in the scribe lines).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL D SCHNASE whose telephone number is (703)756-1691. The examiner can normally be reached Monday - Friday 8:30 AM - 5:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tarifur Chowdhury can be reached at (571) 272-2287. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL SCHNASE/Examiner, Art Unit 2877
/TARIFUR R CHOWDHURY/Supervisory Patent Examiner, Art Unit 2877
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