CTNF 19/041,131 CTNF 99035 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Preliminary Amendment This office action is in response to Preliminary amendment filed on 04/21/2025. In this amendment, claims 1, 10, and 14 are amended. Claims 1-20 have been examined. Information Disclosure Statement The information disclosure statement (IDS) submitted on 01/30/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting 08-30 AIA A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co. , 151 U.S. 186 (1894); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert , 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. 08-31 AIA Claim s 1-13 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claim s 1-13 of prior U.S. Patent No. 11204826 . This is a statutory double patenting rejection. 19041131 US 11204826 1. A memory device, comprising: a plurality of memory macros, each including an array of memory cells, and a first error correction code (ECC) circuit configured to receive data from the respective memory macro and carry out a subset of steps in an error detection and correction operation by detecting data errors in the received data; and a second ECC circuit remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros, and configured to receive the detected data errors from each of the first ECC circuits of the plurality of memory macros and carry out remainder steps of the error detection and correction operation, the remainder steps including correcting the data errors, and writing the corrected data to the array of memory cells in the memory macro, the first ECC circuit being further configured to determine that no error is detected in the received data by the first ECC circuit and, in response to the determination, end the error detection and correction operation for the received data. 1. A memory device, comprising: a plurality of memory macros, each including an array of memory cells, and a first error correction code (ECC) circuit configured to receive data from the respective memory macro and carry out a subset of steps in an error detection and correction operation by detecting data errors in the received data; and a second ECC circuit remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros, and configured to receive the detected data errors from each of the first ECC circuits of the plurality of memory macros and carry out remainder steps of the error detection and correction operation, the remainder steps including correcting the data errors, and writing the corrected data to the array of memory cells in the memory macro, the first ECC circuit being further configured to end the error detection and correction operation for the received data when the first ECC circuit detects no error in the received data. 2. The memory device of claim 1, wherein the memory macros each comprise a magnetic random access memory (MRAM) macro. 2. The memory device of claim 1, wherein the memory macros each comprise a magnetic random access memory (MRAM) macro. 3. The memory device of claim 2, wherein the MRAM macros each further comprise: an array of MRAM bit cells, each MRAM bit cell comprising: a magnetic tunnel junction element; an access transistor coupled to the magnetic tunnel junction element; a first bit line coupled to the access transistor; a second bit line coupled to the magnetic tunnel junction element; a word line coupled to the gate of the access transistor; and local input-output circuitry coupled to the first and second bit lines of the MRAM bit cells. 3. The memory device of claim 2, wherein the MRAM macros each further comprise: an array of MRAM bit cells, each MRAM bit cell comprising: a magnetic tunnel junction element; an access transistor coupled to the magnetic tunnel junction element; a first bit line coupled to the access transistor; a second bit line coupled to the magnetic tunnel junction element; a word line coupled to the gate of the access transistor; and local input-output circuitry coupled to the first and second bit lines of the MRAM bit cells. 4. The memory device of claim 3, wherein the first ECC circuit comprises: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an error check circuit coupled to outputs of each of the first syndrome s1 generator and the second syndrome s3 generator. 4. The memory device of claim 3, wherein the first ECC circuit comprises: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an error check circuit coupled to outputs of each of the first syndrome s1 generator and the second syndrome s3 generator. 5. The memory device of claim 4, wherein the second ECC circuit comprises: an encoder (EN) calculation circuit coupled to the local input-output circuitry; a syndrome s 1 ^ 3 calculation circuit coupled to the output of the first syndrome s1 generator; a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^ 3 generator and the output of the second syndrome s3 generator; a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the MRAM cells with an error. 5. The memory device of claim 4, wherein the second ECC circuit comprises: an encoder (EN) calculation circuit coupled to the local input-output circuitry; a syndrome s 1 ^ 3 calculation circuit coupled to the output of the first syndrome s1 generator; a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^ 3 generator and the output of the second syndrome s3 generator; a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the MRAM cells with an error. 6. The memory device of claim 3, wherein the first ECC circuit comprises: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an EN calculation circuit coupled to the local input-output circuitry; a syndrome s 1 ^ 3 calculation circuit coupled to the output of the first syndrome s1 generator; an error check circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s 1 ^ 3 calculation circuit. 6. The memory device of claim 3, wherein the first ECC circuit comprises: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an EN calculation circuit coupled to the local input-output circuitry; a syndrome s 1 ^ 3 calculation circuit coupled to the output of the first syndrome s1 generator; an error check circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s 1 ^ 3 calculation circuit. 7. The memory device of claim 6, wherein the second ECC circuit comprises: a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^ 3 generator and the output of the second syndrome s3 generator; a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the MRAM cells with an error. 7. The memory device of claim 6, wherein the second ECC circuit comprises: a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^ 3 generator and the output of the second syndrome s3 generator; a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the MRAM cells with an error. 8. The memory device of claim 3, wherein the first ECC circuit comprises: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an EN calculation circuit coupled to the local input-output circuitry; a syndrome s 1 ^ 3 calculation circuit coupled to the output of the first syndrome s1 generator; an error check circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1^3 calculation circuit; a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^ 3 generator and the output of the second syndrome s3 generator; and a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit. 8. The memory device of claim 3, wherein the first ECC circuit comprises: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an EN calculation circuit coupled to the local input-output circuitry; a syndrome s 1 ^ 3 calculation circuit coupled to the output of the first syndrome s1 generator; an error check circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1^3 calculation circuit; a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^ 3 generator and the output of the second syndrome s3 generator; and a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit. 9. The memory device of claim 8, wherein the second ECC circuit comprises: an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the MRAM cells with an error. 9. The memory device of claim 8, wherein the second ECC circuit comprises: an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the MRAM cells with an error. 10. An ECC system comprising: a plurality of first ECC circuits, each of the plurality of first ECC circuits configured to be communicatively coupled to a respective memory array and configured to receive data from the respective memory array and carry out a subset of steps in an error detection and correction operation by detecting data errors in the received data; and a second ECC circuit communicatively coupled to each of the plurality of first ECC circuits and configured to receive the detected data errors from each of the plurality of first ECC circuits and correct the data errors and carry out remainder steps of the error detection and correction operation, the remainder steps including correcting the data errors and writing the corrected data to the respective memory macro, the first ECC circuit being further configured to determine that no error in the received data is detected by the first ECC circuit and, in response to the determination, end the error detection and correction operation for the received data. 10. An ECC system comprising: a plurality of first ECC circuits, each of the plurality of first ECC circuits configured to be communicatively coupled to a respective memory array and configured to receive data in from the respective memory array and carry out a subset of steps in an error detection and correction operation by detecting data errors in the received data; and a second ECC circuit communicatively coupled to each of the plurality of first ECC circuits and configured to receive the detected data errors from each of the plurality of first ECC circuits and correct the data errors and carry out remainder steps of the error detection and correction operation, the remainder steps including correcting the data errors and writing the corrected data to the respective memory macro, the first ECC circuit being further configured to end the error detection and correction operation for the received data when the first ECC circuit detects no error in the received data. 11. The ECC system of claim 10, each of the plurality of first ECC circuits comprising: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; and an error check circuit coupled to the output of each of the first syndrome s1 generator and the second syndrome s3 generator; and the second ECC circuit comprising: an EN calculation circuit coupled to the local input-output circuitry; a syndrome s1^3 calculation circuit coupled to the output of the first syndrome s1 generator; a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^3 generator and the output of the second syndrome s3 generator; a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the memory cells having an error. 11. The ECC system of claim 10, each of the plurality of first ECC circuits comprising: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; and an error check circuit coupled to the output of each of the first syndrome s1 generator and the second syndrome s3 generator; and the second ECC circuit comprising: an EN calculation circuit coupled to the local input-output circuitry; a syndrome s1^3 calculation circuit coupled to the output of the first syndrome s1 generator; a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^3 generator and the output of the second syndrome s3 generator; a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the memory cells having an error. 12. The ECC system of claim 10, each of the plurality of first ECC circuits comprising: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an EN calculation circuit coupled to the local input-output circuitry; a syndrome s1^3 calculation circuit coupled to the output of the first syndrome s1 generator; and an error check circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3, the EN calculation circuit, and the syndrome s1^3 calculation circuit; the second ECC circuit comprising: a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^3 generator and the output of the second syndrome s3 generator; a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the memory cells having an error. 12. The ECC system of claim 10, each of the plurality of first ECC circuits comprising: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an EN calculation circuit coupled to the local input-output circuitry; a syndrome s1^3 calculation circuit coupled to the output of the first syndrome s1 generator; and an error check circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3, the EN calculation circuit, and the syndrome s1^3 calculation circuit; the second ECC circuit comprising: a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^3 generator and the output of the second syndrome s3 generator; a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the memory cells having an error. 13. The ECC system of claim 10, each of the plurality of first ECC circuits comprising: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an EN calculation circuit coupled to the local input-output circuitry; a syndrome s1^3 calculation circuit coupled to the output of the first syndrome s1 generator; an error check circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3, the EN calculation circuit, and the syndrome s1^3 calculation circuit; a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^3 generator and the output of the second syndrome s3 generator; and a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; the second ECC circuit comprising: an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the memory cells having an error. 13. The ECC system of claim 10, each of the plurality of first ECC circuits comprising: a first syndrome s1 generator coupled to the first and second bit lines; a second syndrome s3 generator coupled to the first and second bit lines; an EN calculation circuit coupled to the local input-output circuitry; a syndrome s1^3 calculation circuit coupled to the output of the first syndrome s1 generator; an error check circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3, the EN calculation circuit, and the syndrome s1^3 calculation circuit; a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator; a syndrome comparator coupled to the output of the syndrome s 1 ^3 generator and the output of the second syndrome s3 generator; and a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; the second ECC circuit comprising: an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and a check bit generator circuit to correct the memory cells having an error. 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 14-20 of U.S. Patent No. 11204826 . Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the claimed invention are fully contained in the patented case. See table below. Therefore, the pending claims would have been obvious to a person having ordinary skill in the art at the time this invention was made, given the patented claims . 19041131 US 11204826 14. A method, comprising: providing a plurality of memory macros, each including an array of memory cells and a first ECC circuit; providing a second ECC circuit remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros; refreshing the memory arrays, including carrying out an error detection and correction operation, including carrying out a subset of steps in an error detection and correction operation by checking for data errors in the memory arrays with the first ECC circuits in the respective memory macros; making a first determination that if at least one data error is detected by at least one of the plurality of the first ECC circuits; and, in response to the first determination, carrying out the remainder steps of the error detection and correction operation, the remainder steps including: forwarding the detected data errors from the first ECC circuit to the second ECC circuit; correcting the data error by the second ECC circuit; and writing the corrected data to the respective memory array; and making a second determination that no data error is detected by any of the plurality of the first ECC circuits and in response to the second determination, ending the error detection and correction operation for the respective memory macro. 14. A method, comprising: providing a plurality of memory macros, each including an array of memory cells and a first ECC circuit; providing a second ECC circuit remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros; refreshing the memory arrays, including carrying out an error detection and correction operation, including carrying out a subset of steps in an error detection and correction operation by checking for data errors in the memory arrays with the first ECC circuits in the respective memory macros; if any data error is detected by one of the plurality of the first ECC circuits, carrying out remainder steps of the error detection and correction operation, the remainder steps including: forwarding the detected data errors from the first ECC circuit to the second ECC circuit; correcting the data error by the second ECC circuit; and writing the corrected data to the respective memory array; and if no data error is detected by one of the plurality of the first ECC circuits, ending the error detection and correction operation for the respective memory macro. 15. The method of claim 14, wherein checking for data errors in the MRAM array with the first ECC circuits comprises: generating a syndrome s1 based on data received from the MRAM array; generating a syndrome s3 based on data received from the MRAM array; and error checking based on the syndrome s1 and the syndrome s3. 15. The method of claim 14, wherein checking for data errors in the MRAM array with the first ECC circuits comprises: generating a syndrome s1 based on data received from the MRAM array; generating a syndrome s3 based on data received from the MRAM array; error checking based on the syndrome s1 and the syndrome s3. 16. The method of claim 15, wherein correcting the data error with the second ECC circuit comprises: generating an EN based on data received from the MRAM array; generating a syndrome s 1 ^ 3 based on the syndrome s1; generating a syndrome s1 inversion based on the syndrome s1; comparing the syndrome s 1 ^ 3 and the syndrome s3; generating a GF multi calculation based on the syndrome s1 inversion and the comparison of the syndrome s 1 ^ 3 and the syndrome s3; generating a check bit error correction based on the EN, the syndrome s1, and the GF multi calculation; and writing the check bit error correction to the MRAM array to correct the error. 16. The method of claim 15, wherein correcting the data error with the second ECC circuit comprises: generating an EN based on data received from the MRAM array; generating a syndrome s 1 ^ 3 based on the syndrome s1; generating a syndrome s1 inversion based on the syndrome s1; comparing the syndrome s 1 ^ 3 and the syndrome s3; generating a GF multi calculation based on the syndrome s1 inversion and the comparison of the syndrome s 1 ^ 3 and the syndrome s3; generating a check bit error correction based on the EN, the syndrome s1, and the GF multi calculation; and writing the check bit error correction to the MRAM array to correct the error. 17. The method of claim 14, wherein checking for data errors in the MRAM array with the first ECC circuits comprises: generating a syndrome s1 based on data received from the MRAM array; generating a syndrome s3 based on data received from the MRAM array; generating an EN based on data received from the MRAM array; generating a syndrome s 1 ^ 3 based on the syndrome s1; and error checking based on the syndrome s1, the syndrome s3, the EN, and the syndrome s 1 ^3. 17. The method of claim 14, wherein checking for data errors in the MRAM array with the first ECC circuits comprises: generating a syndrome s1 based on data received from the MRAM array; generating a syndrome s3 based on data received from the MRAM array; generating an EN based on data received from the MRAM array; generating a syndrome s 1 ^ 3 based on the syndrome s1; and error checking based on the syndrome s1, the syndrome s3, the EN, and the syndrome s 1 ^3. 18. The method of claim 17, wherein correcting the data error with the second ECC circuit comprises: generating a syndrome s1 inversion based on the syndrome s1; comparing the syndrome s 1 ^ 3 and the syndrome s3; generating a GF multi calculation based on the syndrome s1 inversion and the comparison of the syndrome s 1 ^ 3 and the syndrome s3; generating a check bit error correction based on the EN, the syndrome s1, and the GF multi calculation; and writing the check bit error correction to the MRAM array to correct the error. 18. The method of claim 17, wherein correcting the data error with the second ECC circuit comprises: generating a syndrome s1 inversion based on the syndrome s1; comparing the syndrome s 1 ^ 3 and the syndrome s3; generating a GF multi calculation based on the syndrome s1 inversion and the comparison of the syndrome s 1 ^ 3 and the syndrome s3; generating a check bit error correction based on the EN, the syndrome s1, and the GF multi calculation; and writing the check bit error correction to the MRAM array to correct the error. 19. The method of claim 14, wherein checking for data errors in the MRAM array with the first ECC circuits comprises: Generating a syndrome s1 based on data received from the MRAM array; generating a syndrome s3 based on data received from the MRAM array; generating an EN based on data received from the MRAM array; generating a syndrome s 1 ^ 3 based on the syndrome s1; error checking based on the syndrome s1, the syndrome s3, the EN, and the syndrome s 1 ^ 3 ; generating a syndrome s1 inversion based on the syndrome s1;comparing the syndrome s 1 ^ 3 and the syndrome s3; and generating a GF multi calculation based on the syndrome s1 inversion and the comparison of the syndrome s 1 ^ 3 and the syndrome s3. 19. The method of claim 14, wherein checking for data errors in the MRAM array with the first ECC circuits comprises: Generating a syndrome s1 based on data received from the MRAM array; generating a syndrome s3 based on data received from the MRAM array; generating an EN based on data received from the MRAM array; generating a syndrome s 1 ^ 3 based on the syndrome s1; error checking based on the syndrome s1, the syndrome s3, the EN, and the syndrome s 1 ^ 3 ; generating a syndrome s1 inversion based on the syndrome s1;comparing the syndrome s 1 ^ 3 and the syndrome s3; and generating a GF multi calculation based on the syndrome s1 inversion and the comparison of the syndrome s 1 ^ 3 and the syndrome s3. 20. The method of claim 19, wherein correcting the data error with the second ECC circuit comprises: Generating a check bit error correction based on the EN, the syndrome s1, and the GF multi calculation; and writing the check bit error correction to the MRAM array to correct the error. 20. The method of claim 19, wherein correcting the data error with the second ECC circuit comprises: Generating a check bit error correction based on the EN, the syndrome s1, and the GF multi calculation; and writing the check bit error correction to the MRAM array to correct the error. Closest Prior Arts of Record Anzou (US Pat. Pub. 20190295680) discloses a memory macro that includes a first ECC circuit configured to generate a code corresponding to input data. Anzou further discloses a second ECC cicuit configured to execute, based on code from the first ECC circuit, error detection or correction of the data. Examiner’s Note There are no prior art(s) rejections in this Office Action. However, examiner will further consider and update search to determine merits of the claims once Applicants fix the above statutory and nonstatutory double patent rejections. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A YANG whose telephone number is (703)756-1447. The examiner can normally be reached Monday - Friday 8:30 a.m. - 5:30 p.m. EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEFFREY ANDREW YANG/Examiner, Art Unit 2111 /MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111 Application/Control Number: 19/041,131 Page 2 Art Unit: 2111 Application/Control Number: 19/041,131 Page 3 Art Unit: 2111 Application/Control Number: 19/041,131 Page 4 Art Unit: 2111 Application/Control Number: 19/041,131 Page 5 Art Unit: 2111 Application/Control Number: 19/041,131 Page 6 Art Unit: 2111 Application/Control Number: 19/041,131 Page 7 Art Unit: 2111 Application/Control Number: 19/041,131 Page 8 Art Unit: 2111 Application/Control Number: 19/041,131 Page 9 Art Unit: 2111 Application/Control Number: 19/041,131 Page 10 Art Unit: 2111 Application/Control Number: 19/041,131 Page 11 Art Unit: 2111 Application/Control Number: 19/041,131 Page 12 Art Unit: 2111 Application/Control Number: 19/041,131 Page 13 Art Unit: 2111 Application/Control Number: 19/041,131 Page 14 Art Unit: 2111 Application/Control Number: 19/041,131 Page 15 Art Unit: 2111 Application/Control Number: 19/041,131 Page 16 Art Unit: 2111 Application/Control Number: 19/041,131 Page 17 Art Unit: 2111 Application/Control Number: 19/041,131 Page 18 Art Unit: 2111 Application/Control Number: 19/041,131 Page 19 Art Unit: 2111 Application/Control Number: 19/041,131 Page 20 Art Unit: 2111 Application/Control Number: 19/041,131 Page 21 Art Unit: 2111 Application/Control Number: 19/041,131 Page 22 Art Unit: 2111 Application/Control Number: 19/041,131 Page 23 Art Unit: 2111 Application/Control Number: 19/041,131 Page 24 Art Unit: 2111 Application/Control Number: 19/041,131 Page 25 Art Unit: 2111 Application/Control Number: 19/041,131 Page 26 Art Unit: 2111 Application/Control Number: 19/041,131 Page 27 Art Unit: 2111 Application/Control Number: 19/041,131 Page 28 Art Unit: 2111 Application/Control Number: 19/041,131 Page 29 Art Unit: 2111 Application/Control Number: 19/041,131 Page 30 Art Unit: 2111 Application/Control Number: 19/041,131 Page 31 Art Unit: 2111 Application/Control Number: 19/041,131 Page 32 Art Unit: 2111 Application/Control Number: 19/041,131 Page 33 Art Unit: 2111 Application/Control Number: 19/041,131 Page 34 Art Unit: 2111 Application/Control Number: 19/041,131 Page 35 Art Unit: 2111 Application/Control Number: 19/041,131 Page 36 Art Unit: 2111 Application/Control Number: 19/041,131 Page 37 Art Unit: 2111 Application/Control Number: 19/041,131 Page 38 Art Unit: 2111 Application/Control Number: 19/041,131 Page 39 Art Unit: 2111 Application/Control Number: 19/041,131 Page 40 Art Unit: 2111 Application/Control Number: 19/041,131 Page 41 Art Unit: 2111 Application/Control Number: 19/041,131 Page 42 Art Unit: 2111 Application/Control Number: 19/041,131 Page 43 Art Unit: 2111 Application/Control Number: 19/041,131 Page 44 Art Unit: 2111 Application/Control Number: 19/041,131 Page 45 Art Unit: 2111 Application/Control Number: 19/041,131 Page 46 Art Unit: 2111 Application/Control Number: 19/041,131 Page 47 Art Unit: 2111 Application/Control Number: 19/041,131 Page 48 Art Unit: 2111 Application/Control Number: 19/041,131 Page 49 Art Unit: 2111 Application/Control Number: 19/041,131 Page 50 Art Unit: 2111 Application/Control Number: 19/041,131 Page 51 Art Unit: 2111 Application/Control Number: 19/041,131 Page 52 Art Unit: 2111 Application/Control Number: 19/041,131 Page 53 Art Unit: 2111 Application/Control Number: 19/041,131 Page 54 Art Unit: 2111 Application/Control Number: 19/041,131 Page 55 Art Unit: 2111 Application/Control Number: 19/041,131 Page 56 Art Unit: 2111 Application/Control Number: 19/041,131 Page 57 Art Unit: 2111 Application/Control Number: 19/041,131 Page 58 Art Unit: 2111 Application/Control Number: 19/041,131 Page 59 Art Unit: 2111 Application/Control Number: 19/041,131 Page 60 Art Unit: 2111 Application/Control Number: 19/041,131 Page 61 Art Unit: 2111 Application/Control Number: 19/041,131 Page 62 Art Unit: 2111 Application/Control Number: 19/041,131 Page 63 Art Unit: 2111 Application/Control Number: 19/041,131 Page 64 Art Unit: 2111 Application/Control Number: 19/041,131 Page 65 Art Unit: 2111 Application/Control Number: 19/041,131 Page 66 Art Unit: 2111
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