DETAILED ACTION
The action is responsive to the following communications: the Application filed February 03, 2025, and the information disclosure statement (IDS) filed February 03, 2025. This application is a CON of 18/156,625.
Claims 1-20 are pending. Claims 1, 8 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 03, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,219,755. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,219,755
Comment
Claim 1. An integrated circuit (IC) device comprising:
an active area extending in a first direction in a substrate;
first and second transistors comprising respective first and second gates and respective first and second portions of the active area;
an anti-fuse device comprising a third portion of the active area between and adjacent to each of the first and second portions of the active area; and
a first conductive element extending in the first direction and overlying and electrically connected to each of the first gate and the second gate.
Claim 1. An integrated circuit (IC) device comprising:
an active area positioned in a substrate;
first and second contact structures overlying and electrically connected to the active area;
a conductive element overlying and electrically connected
to each of the first and second contact structures;
an anti-fuse transistor device comprising a dielectric layer
between a gate structure and the active area;
a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure; and
a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.
Note footnote1
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Park (US 9,196,377) in view of Takaoka (2018/0005704).
Regarding independent claims 1, 8 and 15, Park teaches an integrated circuit (IC) device comprising:
an active area (FIGS. 1-2 and 5: 110S and 210S) extending in a first direction in a substrate (FIG. 5: 102);
first (FIG. 5: 120 transistor) and second (220 transistor) transistors comprising respective first (120) and second gates (220) and respective first (110S) and second (210S) portions of the active area;
an anti-fuse device (FIG. 5: 320 anti-fuse) comprising a third portion of the active area (FIGS. 1-2: 110P) between and adjacent to each of the first and second portions of the active area (see FIG. 5 along with FIGS. 1-2).
a first conductive element (FIG. 13: WL) extending in the first direction (see horizontal and vertical directions) and overlying and electrically connected to each of the first gate and the second gate (421 and 422).
Kim’s a first conductive element does not clearly disclose a physical design of the integrated circuit device.
Takaoka teaches the deficiencies in e.g., FIGS. 1-2 and accompanying disclosure, i.e., a first conductive element (FIGS. 1-2: WL0) extending in the first direction (horizontal, i.e., direction of elements positioned) and overlying and electrically connected to each of the first gate (MC00, ST) and the second gate (MC01 ST, i.e., anti-fuse device, MC00, FU, positioned between first transistor MC00, ST and second transistor MC01, ST).
Park and Takaoka are analogous art because they both are directed to anti-fuse device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park with the specified features of Takaoka because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Takaoka to the teaching of Park such that a memory, as taught by Park, utilizes a conductive element, as taught by Takaoka, for the purpose of enabling selection transistors by electrically connected conductive elements.
Further, regarding method claim 15, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
Regarding claim 2, Park and Takaoka, as combined, teach the limitations of claim 1.
Takaoka further teaches a first via positioned between and electrically connected to the first conductive element and the first gate; and a second via positioned between and electrically connected to the first conductive element and the second gate (para. 0060.
Regarding claim 3, Park and Takaoka, as combined, teach the limitations of claim 1.
Park and Takaoka further teach the anti-fuse device comprises a third gate, and the first conductive element overlies the third gate (Park’s FIG. 13, Takaoka’s FIG. 1, and accompanying disclosure).
Regarding claim 4, Park and Takaoka, as combined, teach the limitations of claim 3.
Takaoka further teaches the anti-fuse device further comprises a dielectric layer positioned between the third gate and the third portion of the active area (see FIGS. 2-3).
Regarding claims 5, 9 and 12, and 16-17, Park and Takaoka, as combined, teach the limitations of claims 1, 8 and 15, respectively.
Park does not explicitly disclose a first contact overlying and electrically connected to the active area adjacent to the first portion of the active area; a second contact overlying and electrically connected to the active area adjacent to the second portion of the active area; and a second conductive element overlying and electrically connected to each of the first contact and the second contact.
However, contracts (or vias) overlying and electrically connecting two portions of elements are a well-known technology for a type of memory layout for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize contacts for connection because these conventional technology are well established in the art of the memory devices
Regarding claim 6, Park and Takaoka, as combined, teach the limitations of claim 1.
Park and Takaoka further teach the active area comprises: a first source/drain (S/D) structure positioned between the first portion and the third portion; and a second S/D structure positioned between the second portion and the third portion (Park’s FIGS. 5-6 and Takaoka’s FIGS. 2-3 and 15, and accompanying disclosure; further it’s an inherent characteristic).
Regarding claim 7, Park and Takaoka, as combined, teach the limitations of claim 1.
Park further teaches each of the first and second transistors comprises an n-type transistor (FIG. 10).
Regarding claim 10, Park and Takaoka, as combined, teach the limitations of claim 8.
Park and Takaoka further teach the first anti-fuse device comprises a fifth gate, the second anti-fuse device comprises a sixth gate, the first conductive element overlies the fifth gate, and the second conductive element overlies the sixth gate (Park’s FIGS. 15-20, Takaoka’s FIG. 1, and accompanying disclosure).
Regarding claim 11, Park and Takaoka, as combined, teach the limitations of claim 10.
Takaoka further teaches the first anti-fuse device further comprises a first dielectric layer positioned between the fifth gate and the fifth portion of the active area, and the second anti-fuse device further comprises a second dielectric layer positioned between the sixth gate and the sixth portion of the active area (see FIGS. 2-3).
Regarding claims 13-14, Park and Takaoka, as combined, teach the limitations of claim 12.
Park and Takaoka further teach the first conductive element and the second conductive element are aligned in the first direction parallel to the third conductive element; and the first conductive element extends in the first direction offset from a first side of the third conductive element, and the second conductive element extends in the first direction offset from a second side of the third conductive element opposite the first side (Park’s FIG. 20 and Takaoka’s FIG. 15).
Allowable Subject Matter
Claims 18-20 are rejected but would be allowable if overcoming nonstatutory double patenting as indicated above rejection, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 8 and 15, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights