DETAILED ACTION
1. Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
3. The information disclosure statement filed on April 9, 2026 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 112
4. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
5. Claim 10 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The claim recites the limitation “adjacent ones of the plurality of first memory cells are commonly connected to a common memory resistor.” This limitation requires memory cells with two adjacent memory cells to be commonly connected to two common memory resistors, one on each side. There’s no disclosure of memory transistors with two common memory resistors.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1, 3-4, 9, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pat. No. 12,277,990 (“Chang”).
8. With respect to claim 1, Chang discloses a memory device (FIG. 1, 100), comprising:
a memory array (104, rows WLm–WL1) including a plurality of first memory cells (103) physically arranged over a plurality of rows and a plurality of first columns,
wherein each of the plurality of first memory cells includes a memory transistor serially coupled to a memory resistor (342 is serially coupled to 372; also note that 352 is serially coupled to 372 through 342); and
one additional row (WL0) arranged next to the memory array,
wherein the one additional row includes a plurality of first shunt components (FIG. 3, M1-M6; the examiner notes that while Chang does not call these components “shunt components”, they are structurally indistinguishable from the claimed “shunt components”), and
wherein each of the plurality of first shunt components includes a shunt transistor (322) and a shunt resistor (362);
wherein respective first source/drain terminals of the shunt transistors of the plurality of first shunt components are electrically coupled to one another (both terminals of each of the transistors in row 0, i.e., WL0, are connected other terminals of other transistors in the memory array, for example all transistor terminals of word line 0 are electrically coupled in series through transistors 342, 344 … 342n, 344n and resistors 372, 274 … 372n, 374n), and respective second source/drain terminals of the shunt transistors of the plurality of first shunt components are electrically coupled to one another and further electrically coupled to respective first source/drain terminals of the memory transistors of the plurality of first memory cells (transistor terminals of word line 0 are connected to transistors of other word lines through bit lines BL0-BLm, bit lines are also electrically coupled to other bit lines through SG transistors 302, 304 … 302n, 304n and mux transistors 382 … 382n).
9. With respect to claim 3, Chang discloses the memory device of claim 1, wherein the memory array further includes a plurality of second memory cells (see FIG. 3A, M4 and M8) arranged over the plurality of rows and a plurality of second columns, wherein each of the plurality of second memory cells includes a memory transistor (344) serially connected to a memory resistor (374).
10. With respect to claim 4, Chang discloses the memory device of claim 3, wherein the one additional row further includes a plurality of second shunt components (M2, M6), wherein each of the plurality of second shunt components includes a shunt transistor (324) and a shunt resistor (364), and wherein respective first source/drain terminals of the shunt transistors of the plurality of second shunt components are electrically coupled to one another, and respective second source/drain terminals of the shunt transistors of the plurality of second shunt components are electrically coupled to one another and further electrically coupled to respective first source/drain terminals of the memory transistors of the plurality of second memory cells (see the rejection of claim 1 above, all transistor terminals are electrically coupled to other terminals through other transistors and resistors).
11. With respect to claim 10, Chang discloses the memory device of claim 1, wherein the plurality of first memory cells each include a magnetoresistive random access memory (MRAM) cell (4:48-51), a resistive random access memory (RRAM) cell, or a phase change random access memory (PCRAM) cell.
12. With respect to claim 11, see the rejection of claims 1, 3, and 4 above.
13. Claims 1, 3-6, 9, 11-16, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. 2009/0225586 (“Ueda”).
14. With respect to claim 1, Ueda discloses a memory device (FIG. 7), comprising:
a memory array (MCA + RCA, rows WL–WL3) including a plurality of first memory cells (MC) physically arranged over a plurality of rows and a plurality of first columns (first column and every other column),
wherein each of the plurality of first memory cells (MC) includes a memory transistor (TM) serially coupled to a memory resistor (MRM); and
one additional row (WL4) arranged next to the memory array,
wherein the one additional row includes a plurality of first shunt components (MCs for WL4; the examiner notes that while Ueda does not call these components “shunt components”, they are structurally indistinguishable from the claimed “shunt components”), and
wherein each of the plurality of first shunt components includes a shunt transistor (TM) and a shunt resistor (MRM);
wherein respective first source/drain terminals of the shunt transistors of the plurality of first shunt components are electrically coupled to one another (all source/drain terminals on the left side of MC on the first and every other column are electrically coupled to 22b), and respective second source/drain terminals of the shunt transistors of the plurality of first shunt components are electrically coupled to one another and further electrically coupled to respective first source/drain terminals of the memory transistors of the plurality of first memory cells (right terminals of MC on the first and every other column are electrically coupled to 24b).
15. With respect to claim 3, Ueda discloses the memory device of claim 1, wherein the memory array further includes a plurality of second memory cells arranged over the plurality of rows and a plurality of second columns (memory cells on odd numbered columns), wherein each of the plurality of second memory cells (MC and RC) includes a memory transistor serially connected to a memory resistor.
16. With respect to claim 4, Ueda discloses the memory device of claim 3, wherein the one additional row further includes a plurality of second shunt components (third column MC), wherein each of the plurality of second shunt components includes a shunt transistor and a shunt resistor, and wherein respective first source/drain terminals of the shunt transistors of the plurality of second shunt components are electrically coupled to one another, and respective second source/drain terminals of the shunt transistors of the plurality of second shunt components are electrically coupled to one another and further electrically coupled to respective first source/drain terminals of the memory transistors of the plurality of second memory cells (see the rejection of claim 1 above).
17. With respect to claim 5, Ueda discloses the memory device of claim 1, wherein respective gate terminals of the shunt transistors of the plurality of first shunt components are electrically coupled to one another, and are configured to receive a shunt enable signal (all WL4 transistor gates are coupled to WL4 line and configured to a receive control signal).
18. With respect to claim 6, Ueda discloses the memory device of claim 1, further comprising: a plurality of source lines electrically coupled to one another and physically arranged along the plurality of first columns (see FIG. 7, lines connected to 24b through transistors 23), respectively; wherein each of the plurality of source lines is electrically coupled to the respective first source/drain terminals of the memory transistors of the plurality of first memory cells and to the respective second source/drain terminal of the shunt transistor of the first shunt component, that are arranged along a respective one of the plurality of first columns (FIG. 7).
19. With respect to claim 9, Ueda discloses the memory device of claim 1, wherein the plurality of first memory cells each include a magnetoresistive random access memory (MRAM) cell (paragraph [0011]), a resistive random access memory (RRAM) cell, or a phase change random access memory (PCRAM) cell.
20. With respect to claim 11, see the rejection of claims 1, 3, and 4 above.
21. With respect to claim 12, Ueda discloses the memory device of claim 11, wherein the first source/drain terminal of the first shunt transistor and the first source/drain terminal of the second shunt transistor are electrically coupled to each other with a first metal track (22b, see the rejection of claim 1), the gate terminal of the first shunt transistor and the gate terminal of the second shunt transistor are electrically coupled to each other with a second metal track (WL4), the gate terminal of the first memory transistor and the gate terminal of the second memory transistor are electrically coupled to each other with a third metal track (WL1-WL3), the first source/drain terminal of the first memory transistor is electrically coupled to a fourth metal track (CLS0, first column), and the first source/drain terminal of the second memory transistor is electrically coupled to a fifth metal track (CLS0, third column).
22. With respect to claim 13, Ueda discloses the memory device of claim 12, wherein the fourth metal track and the fifth metal track are arranged in parallel with each other (CLS0 are in parallel with each other), electrically coupled to each other, and formed in a first metallization layer, and wherein the first metal track to the third metal track are arranged in parallel with one another (22b and WL are in parallel) and formed in a second metallization layer.
23. With respect to claim 14, Ueda discloses the memory device of claim 13, wherein the second metal track is configured to receive a shunt enable signal, and the third metal track is configured to receive a word line assertion signal (see the rejection of claim 5 above).
24. With respect to claim 15, Ueda discloses the memory device of claim 14, wherein when the shunt enable signal is provided at a first logic state, the fourth metal track and the fifth metal track are electrically coupled to the first metal track (CLS0 lines are coupled when columns are selected with 21 regardless of the state of WL lines).
25. With respect to claim 16, Ueda discloses the memory device of claim 15, wherein when the shunt enable signal is provided at a second logic state, the fourth metal track and the fifth metal track are electrically decoupled from the first metal track (CSL0 lines are decoupled when columns are not selected regardless of the state of WL lines).
26. With respect to claim 18, see the rejection of claims 11 and 12 above.
27. With respect to claim 19, see the rejection of claim 5 above.
28. With respect to claim 20, see the rejection of claims 15 and 16 above.
Allowable Subject Matter
29. Claims 2 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
30. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571)272-4179. The examiner can normally be reached 9 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on (571) 272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Woo H Choi/
Primary Examiner,
Art Unit 3992
Prosecution Insights