DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hollerbach et al. [US 20200159132 A1] in view of Coskun et al. [US 2018/0329310 A1].
Regarding claims 1-4, 10-12 and 16, Hollerbach et al. discloses a method for processing an apparatus (Figs. 5-7), comprising:
determining one or more altered electrical connections based on an offset between a designed component and an altered component disposed on a substrate (as shown in Fig. 5, 502-510, see also paragraphs [0045]-[0050] determining the altered electrical connections);
performing a photoresist development process, comprising: depositing a photoresist over the substrate; developing the photoresist to form one or more developed regions and one or more undeveloped regions; removing the one or more developed regions or the one or more undeveloped regions of the photoresist to form an altered electrical connection template (as shown in Figs. 6 and 7, 602-612 or 702-714, see also paragraphs [0051]-[0053] teaches the lithographic and development of the altered electrical connections).
Hollerbach et al. does not teach scanning the altered component and the altered electrical connection template to identify one or more misaligned regions of the altered electrical connection template; removing at least a portion of the altered electrical connection template upon identifying the one or more misaligned regions; and repeating the photoresist development process upon identifying one or more misaligned regions; depositing an electrical connection material in the altered electrical connection template; and removing at least a portion of the altered electrical connections template to form an altered layout plot.
However, Coskun et al. discloses a method of freeform distortion correction for reducing distortion errors wherein the exposed image is scanned and measured to determine further distortion and the lithographic process is repeated until all areas are corrected (as shown in Figs. 8 and 11B, see also Claim 4).
Therefore, it would have been obvious to one of ordinary skill in the art to provide a feedback and repeat lithographic process to provide distortion correction, as taught by Coskun et al. in the method of Hollerbach et al. because such a modification provides a method for increasing the accuracy of the distortion correction (paragraph [0032] of Coskun et al.).
Regarding claims 5, 6, 14, 15, 19 and 20, Hollerbach et al. discloses further comprising: comparing a first set of data of a designed component to a second set of data of the altered component; and comparing the offset to a threshold, wherein: when the offset is less than the threshold, setting the offset to zero; and when the offset is greater than the threshold, generating a warning to a user that the threshold has been exceeded, wherein the one or more altered electrical connections is based on the offset (paragraphs [0057]-[0071] teaches comparing the offset to a threshold and setting the offset to zero).
Regarding claims 7 and 17, Hollerbach et al. discloses wherein the method is performed in-situ in a maskless microlithography system (paragraphs [0031] and [0066] teaches maskless microlithography).
Regarding claims 8, 9, 13 and 18, Hollerbach et al. in view of Coskun et al. discloses further comprising providing the one or more altered electrical connections between the altered component and a second altered component, further comprising providing the one or more altered electrical connections between the altered component and a fixed perimeter of the substrate (Figs. 4-7, see also paragraphs [0045]-[0053] of Hollerbach et al. and Figs. 8 and 11B of Coskun et al.).
Conclusion
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/DEORAM PERSAUD/Primary Examiner, Art Unit 2882
