DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 10/01/2025 have been considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Summa et al. (US 20240094751; hereinafter Summa).
Regarding claim 1, Summa discloses in figure(s) 1-5 a testing method for an electronic circuit, comprising:
providing a test voltage signal (VDD_ext @ test device 250 on ICTR ; figs. 2, 3A) to a connection pad (test pad 212; figs. 2, 3A) of the electronic circuit (integrated circuit 202/302);
controlling a voltage regulating circuit (VRC 204*) of the electronic circuit to generate a reference voltage (VDD_int) and providing the reference voltage to the connection pad;
adjusting a voltage value of one of the test voltage signal and the reference voltage (para. 19 - VDD_int is maintained proportional to the reference voltage V.sub.REF by way of the voltage regulator circuitry; paras. 18-21 - generating an output monitoring signal indicating "VDD too high" when the internal supply voltage VDD_int exceeds the high threshold voltage V_HI, or generating an output monitoring signal indicating "VDD too low" when VDD_int falls below the low threshold voltage V_LO; figs. 1-2), and receiving a test current (ICTR; para. 33 - generate a control current having an amplitude within a range of currents represented as +I.sub.CTR and −I.sub.CTR, with the polarity (±) of the control current indicating the direction with respect to the IC chip 202 i.e. sourced out of (−) or sunk into (+) the IC chip 202) flowing through the connection pad; and
determining a measured voltage value (para. 50 - internal supply VDD_int and the control current I.sub.CTR have a linear relationship between one another, such that the internal supply voltage VDD_int is adjusted linearly with changes in the amplitude and polarity of the control current I.sub.CTR) of the reference voltage according to a change in a current direction of the test current (para. 33 - a range of currents represented as +I.sub.CTR and −I.sub.CTR, with the polarity (±) of the control current indicating the direction with respect to the IC chip 202 i.e. sourced out of (−) or sunk into (+) the IC chip 202).
Regarding claim 11, Summa discloses in figure(s) 1-5 a testing device for an electronic circuit, comprising:
a voltage generator (test device 250 on ICTR ; figs. 2, 3A) connected to a connection pad (test pad 212; figs. 2, 3A) of the electronic circuit and configured to provide a test voltage signal (VDD_ext @ test device 250 on ICTR) to the connection pad of the electronic circuit (integrated circuit 202/302);
a controller (VRC 204*) connected to the electronic circuit, and configured to control the electronic circuit to generate a reference voltage (VDD_int) and provide the reference voltage to the connection pad, and adjust a voltage value of one of the test voltage signal and the reference voltage (para. 19 - VDD_int is maintained proportional to the reference voltage V.sub.REF by way of the voltage regulator circuitry; paras. 18-21 - generating an output monitoring signal indicating "VDD too high" when the internal supply voltage VDD_int exceeds the high threshold voltage V_HI, or generating an output monitoring signal indicating "VDD too low" when VDD_int falls below the low threshold voltage V_LO; figs. 1-2); and
a current sensor connected to the connection pad and configured to receive a test current (ICTR; para. 33 - generate a control current having an amplitude within a range of currents represented as +I.sub.CTR and −I.sub.CTR, with the polarity (±) of the control current indicating the direction with respect to the IC chip 202 i.e. sourced out of (−) or sunk into (+) the IC chip 202) flowing through the connection pad, wherein the controller determines a measured voltage value (para. 50 - internal supply VDD_int and the control current I.sub.CTR have a linear relationship between one another, such that the internal supply voltage VDD_int is adjusted linearly with changes in the amplitude and polarity of the control current I.sub.CTR) of the reference voltage according to a change in a current direction of the test current (para. 33 - a range of currents represented as +I.sub.CTR and −I.sub.CTR, with the polarity (±) of the control current indicating the direction with respect to the IC chip 202 i.e. sourced out of (−) or sunk into (+) the IC chip 202).
Claim(s) 1-2, 5, 7-12, 15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by YOO et al. (US 20150054532; hereinafter YOO).
Regarding claim 1, YOO discloses in figure(s) 1-17 a testing method for an electronic circuit, comprising:
providing a test voltage signal (SV; fig. 7) to a connection pad (TP) of the electronic circuit (DUT 230);
controlling (@211,410) a voltage regulating circuit (210,231,232) of the electronic circuit to generate a reference voltage (applied voltage @ TP [Wingdings font/0xE0] NRV=VDD-VD, AIRV=-VD, ADRV=∞ in fig. 8) and providing the reference voltage (voltage from 13 to 5) to the connection pad;
adjusting a voltage value of one of the test voltage signal and the reference voltage, and receiving a test current (IT) flowing through the connection pad; and
determining a measured voltage value (measured response VTR) of the reference voltage according to a change in a current direction of the test current (para. 60 - if the direction of the test current IT is from the device under test DUT toward the test unit 200, the test response voltage VTR measured in the test pad TP may be a positive voltage level. If the test response voltage VTR is a positive voltage level, the circuit inside the device may not be broken; para. 59 - if the direction of the test current IT is from the device under test DUT toward the test unit 200, a circuit of the device that is connected to the test pad TP may be broken).
Regarding claim 2, YOO discloses in figure(s) 1-17 the testing method according to claim 1, wherein a step of adjusting the voltage value of one of the test voltage signal and the reference voltage comprises: fixing the voltage value of the test voltage signal (VDD), and adjusting the voltage value of the reference voltage (applied voltage @ TP [Wingdings font/0xE0] NRV=VDD-VD, AIRV=-VD, ADRV=∞; fig. 8 ).
Regarding claim 5, YOO discloses in figure(s) 1-17 the testing method according to claim 1, wherein a step of adjusting the voltage value of one of the test voltage signal and the reference voltage comprises: fixing the voltage value of the reference voltage (VDD-VD), and adjusting the voltage value of the test voltage signal (VDD/VSS).
Regarding claim 7, YOO discloses in figure(s) 1-17 the testing method according to claim 1, wherein a step of determining the measured voltage value of the reference voltage according to the change in the current direction of the test current comprises: using a voltage value corresponding to the change in the current direction as the measured voltage value (VDD-VD vs. -VD based on IT current direction) of the reference voltage.
Regarding claim 8, YOO discloses in figure(s) 1-17 the testing method according to claim 1, wherein when the voltage value of the test voltage signal (VDD) is higher than the voltage value of the reference voltage (VDD-VD), the test current has a first current direction.
Regarding claim 9, YOO discloses in figure(s) 1-17 the testing method according to claim 8, wherein when the voltage value of the test voltage signal (VSS) is lower than the voltage value of the reference voltage (-VD), the test current has a second current direction opposite to the first current direction.
Regarding claim 11, YOO discloses in figure(s) 1-17 a testing device for an electronic circuit, comprising:
a voltage generator (400; fig. 7) connected to a connection pad (TP) of the electronic circuit and configured to provide a test voltage signal (SV; fig. 7) to the connection pad of the electronic circuit;
a controller (CU 100) connected to the electronic circuit, and configured to control the electronic circuit to generate a reference voltage (applied voltage @ TP [Wingdings font/0xE0] NRV=VDD-VD, AIRV=-VD, ADRV=∞ ) and provide the reference voltage to the connection pad, and adjust a voltage value of one of the test voltage signal and the reference voltage (fig. 8); and
a current sensor connected to the connection pad and configured to receive a test current (IT) flowing through the connection pad (para. 54 - measuring the test response current ITR by applying the test voltage VT to the device under test DUT), wherein the controller determines a measured voltage value (VM 191; para. 54 - measuring the test response voltage VTR by applying the test current IT to the device under test DUT) of the reference voltage according to a change in a current direction of the test current (para. 60 - if the direction of the test current IT is from the device under test DUT toward the test unit 200, the test response voltage VTR measured in the test pad TP may be a positive voltage level. If the test response voltage VTR is a positive voltage level, the circuit inside the device may not be broken; para. 59 - if the direction of the test current IT is from the device under test DUT toward the test unit 200, a circuit of the device that is connected to the test pad TP may be broken).
Regarding claim 12, YOO discloses in figure(s) 1-17 the testing device according to claim11, wherein the controller fixes the voltage value of the test voltage signal (VDD) and adjusts the voltage value of the reference voltage (applied voltage @ TP [Wingdings font/0xE0] NRV=VDD-VD, AIRV=-VD, ADRV=∞; fig. 8 ).
Regarding claim 15, YOO discloses in figure(s) 1-17 the testing device according to claim 11, wherein the controller fixes the voltage value of the reference voltage (VDD-VD) and adjusts the voltage value of the test voltage signal (VDD/VSS).
Regarding claim 17, YOO discloses in figure(s) 1-17 the testing device according to claim 11, wherein the controller uses a voltage value corresponding to the change in the current direction as the measured voltage value of the reference voltage (para. 55 - a direction of the test current IT may be from the test unit 200 toward the device under test DUT or device under test DUT toward the test unit 200).
Regarding claim 18, YOO discloses in figure(s) 1-17 the testing device according to claim 11, wherein when the voltage value of the test voltage signal (VDD) is higher than the voltage value of the reference voltage (VDD-VD), the test current has a first current direction.
Regarding claim 19, YOO discloses in figure(s) 1-17 the testing device according to claim 18, wherein when the voltage value of the test voltage signal (VSS) is lower than the voltage value of the reference voltage (-VD), the test current has a second current direction opposite to the first current direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 6, 13-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over YOO in view of CHOI et al. (US 20110001467).
Regarding claim 3, YOO teaches in figure(s) 1-17 the testing method according to claim 2,
YOO does not teach explicitly wherein the voltage regulating circuit generates the reference voltage in response to a tuning code.
However, CHOI teaches in figure(s) 1-6 wherein the voltage regulating circuit generates the reference voltage in response to a tuning code (CODE[1:n]; fig. 1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of YOO by having wherein the voltage regulating circuit generates the reference voltage in response to a tuning code as taught by CHOI in order to provide "optimizing a driving voltage of an electronic device includes; iteratively varying the level of a driving voltage provided to the electronic device and performing an operation of the electronic device with each iteration until the operation fails, and then selecting as an operating level for the driving voltage, a level of the driving voltage for an iteration just prior to an iteration in which the operation fails" (abstract).
Regarding claim 4, YOO in view of CHOI teaches the testing method according to claim 3,
CHOI additionally teaches in figure(s) 1-6 wherein a step of adjusting the voltage value of the reference voltage comprises: sweeping a code value of the tuning code such that the voltage regulating circuit sweeps the voltage value of the reference voltage (para. 37 - code storage unit 15 of the logic circuit 11 may output sequentially-increasing driving voltage codes to the VR 19, and thus the VR 19 may output sequentially-increasing driving voltages).
Regarding claim 6, YOO teaches in figure(s) 1-17 the testing method according to claim 5,
YOO does not teach explicitly wherein a step of adjusting the voltage value of the test voltage signal comprises: sweeping the voltage value of the test voltage signal.
However, CHOI teaches in figure(s) 1-6 wherein a step of adjusting the voltage value of the test voltage signal comprises: sweeping the voltage value of the test voltage signal (clms. 7,8 - control unit is further configured to provide a test signal to the electronic device during each iteration of varying the driving voltage and receive a response signal from the electronic device in response to the test signal …a voltage regulator configured to provide a plurality of driving voltages that sequentially vary according to the plurality of driving voltage codes).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of YOO by having wherein a step of adjusting the voltage value of the test voltage signal comprises: sweeping the voltage value of the test voltage signal as taught by CHOI in order to provide "iteratively varying the level of a driving voltage provided to the electronic device and performing an operation of the electronic device with each iteration until the operation fails" (clm. 1).
Regarding claim 13, YOO teaches in figure(s) 1-17 the testing device according to claim 12,
YOO does not teach explicitly wherein the controller provides a tuning code, and a voltage regulating circuit of the electronic circuit generates the reference voltage in response to the tuning code.
However, CHOI teaches in figure(s) 1-6 wherein the controller provides a tuning code (CODE[1:n]; fig. 1), and a voltage regulating circuit (VR 19) of the electronic circuit generates the reference voltage in response to the tuning code.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of YOO by having wherein the voltage regulating circuit generates the reference voltage in response to a tuning code as taught by CHOI in order to provide "optimizing a driving voltage of an electronic device includes; iteratively varying the level of a driving voltage provided to the electronic device and performing an operation of the electronic device with each iteration until the operation fails, and then selecting as an operating level for the driving voltage, a level of the driving voltage for an iteration just prior to an iteration in which the operation fails" (abstract).
Regarding claim 14, YOO in view of CHOI teaches the testing device according to claim 13,
CHOI additionally teaches in figure(s) 1-6 wherein the controller sweeps a code value of the tuning code, so that the voltage regulating circuit sweeps the voltage value of the reference voltage (para. 37 - code storage unit 15 of the logic circuit 11 may output sequentially-increasing driving voltage codes to the VR 19, and thus the VR 19 may output sequentially-increasing driving voltages).
Regarding claim 16, YOO teaches in figure(s) 1-17 the testing device according to claim 15,
YOO does not teach explicitly wherein the controller controls the voltage generator to sweep the voltage value of the test voltage signal.
However, CHOI teaches in figure(s) 1-6 wherein the controller controls the voltage generator to sweep the voltage value of the test voltage signal (clms. 7,8 - control unit is further configured to provide a test signal to the electronic device during each iteration of varying the driving voltage and receive a response signal from the electronic device in response to the test signal …a voltage regulator configured to provide a plurality of driving voltages that sequentially vary according to the plurality of driving voltage codes).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of YOO by having wherein a step of adjusting the voltage value of the test voltage signal comprises: sweeping the voltage value of the test voltage signal as taught by CHOI in order to provide "iteratively varying the level of a driving voltage provided to the electronic device and performing an operation of the electronic device with each iteration until the operation fails" (clm. 1).
Claim(s) 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over YOO in view of Manhaeve et al. (US 20030062916).
Regarding claim 10, YOO teaches in figure(s) 1-17 the testing method according to claim 1,
YOO does not teach explicitly wherein when the voltage value of the test voltage signal is equal to the voltage value of the reference voltage, a current value of the test current is equal to 0.
However, Manhaeve teaches in figure(s) 1-12 wherein when the voltage value of the test voltage signal is equal to the voltage value of the reference voltage, a current value of the test current is equal to 0 (para. 61 - current IMIR will be zero when VDD′ equals VDD).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of YOO by having wherein when the voltage value of the test voltage signal is equal to the voltage value of the reference voltage, a current value of the test current is equal to 0 as taught by Manhaeve in order to provide "testing electronic devices via supply current measurements… either on-chip or off-chip. Both static and dynamic (transient) currents" (para. 10).
Regarding claim 20, YOO teaches in figure(s) 1-17 the testing device according to claim 11,
YOO does not teach explicitly wherein when the voltage value of the test voltage signal is equal to the voltage value of the reference voltage, a current value of the test current is equal to 0.
However, Manhaeve teaches in figure(s) 1-12 wherein when the voltage value of the test voltage signal is equal to the voltage value of the reference voltage, a current value of the test current is equal to 0 (para. 61 - current IMIR will be zero when VDD′ equals VDD).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of YOO by having wherein when the voltage value of the test voltage signal is equal to the voltage value of the reference voltage, a current value of the test current is equal to 0 as taught by Manhaeve in order to provide "testing electronic devices via supply current measurements… either on-chip or off-chip. Both static and dynamic (transient) currents" (para. 10).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bourstein et al. (US 20120049873) discloses "testing an electronic device supplying a first voltage output from a voltage regulator to a first power connection terminal of the electronic device to provide power to the electronic device".
Kodera et al. (US 20090015221) discloses "voltage generator regulates the output voltage so that a virtual short circuit is produced in the first operational amplifier. An output capacitor smoothes the output voltage generated by the voltage generating apparatus. A sense signal generator detects a current flowing in the output capacitor and generates a sense signal proportional to the current detected".
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/
Primary Examiner, Art Unit 2858
Prosecution Insights