DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statements (IDS) submitted on February 11, 2025 and October 2, 2025 have been fully considered by the examiner.
Claim Objections
3. Claim 6 and 15 are objected to because of the following informalities.
Claim 6 recites the limitation, “when the read write selection signal is at the first logic level, and the set signal is at a second logic level, the control circuit conducts a set operation to write the input data into all the storage units.” Similarly, claim 15 recites the limitation, “when the read write selection signal is at the first logic level, and the set signal is at a second logic level, conducting a set operation to write the input data into all the storage units.”
Because ¶[0019-0020] and claims 4 and 13 all teach these logic levels result in writing preset data into all the storage units, Examiner believes claims 6 and 15 each contain a typographical error.
Because claim 5, upon which claim 6 depends, has already recited the case in which the set signal is low and input data is written, for this purpose of this action, “when the read write selection signal is at the first logic level, and the set signal is at a second logic level, the control circuit conducts a set operation to write the input data into all the storage units” shall be interpreted as “when the read write selection signal is at the first logic level, and the set signal is at a second logic level, the control circuit conducts a set operation to write the preset data into all the storage units.”
Because claim 14, upon which claim 15 depends, has already recited the case in which the set signal is low and input data is written, for this purpose of this action, “when the read write selection signal is at the first logic level, and the set signal is at a second logic level, conducting a set operation to write the input data into all the storage units” shall be interpreted as “when the read write selection signal is at the first logic level, and the set signal is at a second logic level, conducting a set operation to write the data into all the storage units.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation “the following steps” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the following steps” shall be interpreted as “ steps of”. Claims 12-19 depend on claim 11.
Claim 12 recites the limitation “the step of decoding the address data” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim (“decoding the address data” is stated as a purpose or outcome of the step of receiving address data in claim 11, but not as a separate step).
For the purpose of this action, “the step of decoding the address data” shall be interpreted as “the step of receiving address data to decode the address data”. Claims 13-16 depend on claim 12.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Park, et al (US 6031785 A), hereinafter Park, in view of Nagata (US 20220199153 A1), and further in view of Ashmore, Jr. (US 5267204 A), hereinafter Ashmore.
Regarding independent claim 1, Park teaches a semiconductor memory apparatus, comprising:
a memory array (FIG. 2, 100), having a plurality of memory blocks (FIG. 3, MBK1..MBKq), each of the memory blocks comprising a plurality of storage units (FIG. 4, plurality of CELL 300);
an address input buffer (FIG. 2, 104), configured to receive address data (FIG. 2, address buffer 104 receives an external address);
a decoder (FIG. 2, Column Decoder 106), coupled to the memory array (FIG. 2, via Column Selection Circuit 110) and the address input buffer (FIG. 2, via signals m-k), and configured to decode the address data (Col. 3, ll. 65-67 teaches “The column decoder outputs a signal to column selection circuit 110 for selecting a column of the memory cell array”); and
a control circuit (FIG. 2, 102, 108, 122), coupled to the decoder, and configured to receive a read write selection signal (FIG. 2,
W
E
¯
).
Park does not teach the control circuit is coupled to the decoder, configured to receive a set signal, and to initialize the memory blocks in sequence accordingly.
Nagata teaches a control circuit (FIG. 1, CONT; ¶[0024]), coupled to the decoder (FIG. 4 shows controller CONT coupled to word line drivers WDR, which are shown in FIG. 1 as part of row decoder RDE; ¶[0032]), a set signal (FIGS. 1 and 5, RESET), and to initialize the memory blocks (¶[0045] teaches “When SRAM1 is reset, all memory cells MC in SRAM1 are initialized”).
Ashmore teaches memory blocks are initialized in sequence (FIG. 4a, 156, 172, 174).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Nagata into the method of Park to include an external “set” (RESET) signal to a control circuit. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of initializing the stored data of all memory cells quickly (¶[0038], [0042]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Ashmore into the method of Park to include initializing memory block-by-block in sequence. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of initializing and error checking each block in a memory device before any input data are programmed into the memory device (Col. 6, ll. 36-40).
Regarding claim 10, Park as modified by Nagata and Ashmore teaches the limitations of claim 1.
Nagata further teaches the memory array is a static random access memory array (FIG. 1, ¶[0023]).
8. Claims 2-7 are rejected under 35 U.S.C. 103 as being unpatentable over Park, et al (US 6031785 A), hereinafter Park, in view of Nagata (US 20220199153 A1), further in view of Ashmore, Jr. (US 5267204 A), hereinafter Ashmore, and further in view of Schmitt-Landsiedel, et al (US 5093809 A), hereinafter Schmitt-Landsiedel.
Regarding claim 2, Park as modified by Nagata and Ashmore teaches the limitations of claim 1.
Park does not teach the decoder selects a target memory block from the memory blocks based on a plurality of high-order address bits in the address data.
Schmitt-Landsiedel teaches the decoder selects a target memory block from the memory blocks based on a plurality of high-order address bits in the address data (Col. 4, ll. 47-49 teaches “The uppermost addresses are decoded into block select signals”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Schmitt-Landsiedel into the method of Park to include generating block select signals from the most significant address bits. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of reducing the delay time that results from a high "fan-out" of the multiplexes and decoder circuits on the respective hierarchy level (Schmitt-Landsiedel Col. 7, ll. 5-17).
Regarding claim 3, Park as modified by Nagata, Ashmore, and Schmitt-Landsiedel teaches the limitations of claim 2.
Nagata further teaches a drive and sense circuit, coupled to the decoder and the control circuit (e.g., FIG. 1, word line drivers WDR, FIG. 5, sense amplifier SA; FIGS. 3 and 4 show controller connections to SA and WDR, respectively).
Regarding claim 4, Park as modified by Nagata, Ashmore, and Schmitt-Landsiedel teaches the limitations of claim 3.
Park together with Nagata further teaches when the read write selection signal is at a first logic level (Park’s
W
E
¯
is asserted low for a write – see Col. 1, ll. 1-9)), and the set signal is at a second logic level (Nagata’s RESET signal is asserted high – see FIG. 6), the control circuit conducts a set operation to write preset data (¶[0002] of the present application gives examples of preset data as 00h and FFh) into all the storage units in the target memory block through the drive and sense circuit (Nagata ¶[0029] teaches “When the first bit line BT is set to the write data of the high level ‘1’ and the second bit line BB is set to the write data of the low level ‘0’ and the word line WL is set to the selected level of the high level, the transfer transistors N3 and N4 are turned on and the data of the high level ‘1’ is stored in the memory cell MC,” which results in “preset data” FFh written to the block. This is done by driving the bit lines to their respective levels with buffers WBT and WBB – see FIGS. 1 and 3 and ¶[0054].) within one cycle time (Nagata FIG. 6 shows the RESET initialization operation occurs in one one-shot clock cycle on the CLK line; ¶[0055]).
Regarding claim 5, Park as modified by Nagata, Ashmore, and Schmitt-Landsiedel teaches the limitations of claim 3.
Nagata further teaches a data input/output buffer, coupled to the drive and sense circuit, and configured to receive input data (FIG. 3; ¶[0041] teaches “The write buffer/sense amplifier unit WSP includes a data input circuit DIN to which input data Din to be written to a memory cell selected at the time of normal writing is supplied, and a sense amplifier SA which detects data stored in the memory cell selected at the time of normal reading and outputs the detected data as read data Dout”),
wherein when the read write selection signal and the set signal are at a first logic level (Both Park’s
W
E
¯
and Nagata’s RESET are low), the control circuit conducts a write operation to write the input data into the corresponding storage unit in the target memory block through the drive and sense circuit (¶[0045] teaches reset state is only entered when RESET is high, so normal operating modes including read and write modes may be used when RESET is low; a normal write is done per ¶[0041], which teaches “The data input circuit DIN generates write data DT to the bit line BT and write data DB to the bit line BB based on the input data Din during normal writing. The data DT and BT are supplied to the bit lines BT and BB via the write column switches…”).
Regarding claim 6, Park as modified by Nagata, Ashmore, and Schmitt-Landsiedel teaches the limitations of claim 5.
Park together with Nagata teaches when the read write selection signal is at the first logic level (Park’s
W
E
¯
is asserted low for a write – see Col. 2, ll. 1-9)), and the set signal is at a second logic level (Nagata’s RESET signal is asserted high – see FIG. 6), the control circuit conducts a set operation to write the preset data (see claim objections) into all the storage units in the target memory block through the drive and sense circuit (Nagata ¶[0029] teaches “When the first bit line BT is set to the write data of the high level ‘1’ and the second bit line BB is set to the write data of the low level ‘0’ and the word line WL is set to the selected level of the high level, the transfer transistors N3 and N4 are turned on and the data of the high level ‘1’ is stored in the memory cell MC,” which results in “preset data” FFh written to the block. This is done by driving the bit lines to their respective levels with buffers WBT and WBB – see FIGS. 1 and 3 and ¶[0054].) within one cycle time (Nagata FIG. 6 shows the RESET initialization operation occurs in one one-shot clock cycle on the CLK line; ¶[0055]).
Regarding claim 7, Park as modified by Nagata, Ashmore, and Schmitt-Landsiedel teaches the limitations of claim 5.
Park further teaches when the read write selection signal is at a second logic level (
W
E
¯
is set high for a read), the control circuit conducts a read operation (Col. 1, ll. 56-64 teach “When external write enable signal WE is `H` (i.e., logical `1`)…a burst read cycle begins”) to read data stored in the corresponding storage unit in the target memory block through the drive and sense circuit, and outputs the read data as output data through the data input/output buffer (FIG. 5 shows data from memory cell 300 may be sensed by SSA1 and stored by output buffer SRL1 – see also FIGS. 2-4).
9. Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Park, et al (US 6031785 A), hereinafter Park, in view of Nagata (US 20220199153 A1), further in view of Ashmore, Jr. (US 5267204 A), hereinafter Ashmore, further in view of Suzuki (US 5748558 A), and further in view of Cline, et al (US 4528666 A), hereinafter Cline.
Regarding claim 8, Park as modified by Nagata and Ashmore teaches the limitations of claim 1.
Nagata further teaches the control circuit receives a clock signal (FIG. 5, CLK) and a chip enable signal (FIG. 5, RS).
Park does not teach the control circuit responds to the clock signal to capture logic levels of the read write selection signal, the set signal and the chip enable signal.
Suzuki teaches the control circuit responds to the clock signal to capture logic levels of the read write selection signal and the chip enable signal (FIG. 1, registers 102, 103 clocked by clock signal K; Col. 1, ll. 15-20 teach “An address signal supplied from the external is stored in the address register 101 in synchronous with a clock signal K generated internally based on an external clock signal. Similarly, the SRAM comprises registers 102 and 103 for holding a chip select signal /S and a write signal /W respectively.”)).
Cline teaches the control circuit responds to the clock signal to capture the set signal (FIG. 2; Col. 9, ll. 20-21).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Suzuki into the method of Park to include registers for synchronously capturing exterior control signals. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of generating a plurality of internal control signals based on the external control signals (Suzuki Col. 5, ll. 48-59).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Cline into the method of Park to include a reset flip-flop circuit clocked by an external clock. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of generating a synchronous reset signal from an asynchronous reset signal (Cline Col. 9, ll. 9-21).
Regarding claim 9, Park as modified by Nagata, Ashmore, Suzuki, and Cline teaches the limitations of claim 8.
Nagata further teaches when the chip enable signal is at a second logic level (FIG. 7, RS is high), the semiconductor memory apparatus is in an idle state (¶[0048]).
10. Claims 11 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata (US 20220199153 A1) in view of Park, et al (US 6031785 A), hereinafter Park, and further in view of Ashmore, Jr. (US 5267204 A), hereinafter Ashmore.
Regarding independent claim 11, Nagata teaches a method for initializing a semiconductor memory apparatus (Abstract), wherein the semiconductor memory apparatus (FIG. 1) comprises a memory array (FIG. 1, AR; ¶[0026]) comprising a plurality of storage units (FIG. 1, MC; ¶[0026]), the initialization method comprising the following steps:
receiving address data to decode the address data (¶[0032] teaches “word line decoder RDE includes a row decoder circuit (not shown) that decodes the address signal,” which indicates an address signal has been received); and
receiving a set signal (FIGS. 1 and 5, RESET), and initializing the memory blocks (¶[0045] teaches “When SRAM1 is reset, all memory cells MC in SRAM1 are initialized”).
Nagata does not teach a plurality of memory blocks, receiving a read write selection signal, and initializing the memory blocks in sequence accordingly.
Park teaches teach a plurality of memory blocks (FIG. 3, MBK1..MBKq), and receiving a read write selection signal (FIG. 2,
W
E
¯
).
Ashmore teaches memory blocks are initialized in sequence (FIG. 4a, 156, 172, 174).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Park into the method of Nagata to include a read/write selection signal. The ordinary artisan would have been motivated to modify Nagata in the above manner for the purpose of differentiating between read and write operations (Col. 8, l. 66 – Col. 9, l. 13 (read,
W
E
¯
high) and Col. 9, l. 55 – Col. 10, l. 2 (write,
W
E
¯
low)).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Ashmore into the method of Nagata to include initializing memory block-by-block in sequence. The ordinary artisan would have been motivated to modify Nagata in the above manner for the purpose of initializing and error checking each block in a memory device before any input data are programmed into the memory device (Col. 6, ll. 36-40).
Regarding claim 19, Nagata as modified by Park and Ashmore teaches the limitations of claim 11.
Nagata further teaches the memory array is a static random access memory array (FIG. 1, ¶[0023]).
11. Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata (US 20220199153 A1) in view of Park, et al (US 6031785 A), hereinafter Park, further in view of Ashmore, Jr. (US 5267204 A), hereinafter Ashmore, and further in view of Schmitt-Landsiedel, et al (US 5093809 A), hereinafter Schmitt-Landsiedel.
Regarding claim 12, Nagata as modified by Park and Ashmore teaches the limitations of claim 11.
Nagata does not teach the step of decoding the address data comprises:
selecting a target memory block from the memory blocks based on a plurality of high-order address bits in the address data.
Schmitt-Landsiedel teaches the step of decoding the address data comprises:
selecting a target memory block from the memory blocks based on a plurality of high-order address bits in the address data (Col. 4, ll. 47-49 teaches “The uppermost addresses are decoded into block select signals”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Schmitt-Landsiedel into the method of Nagata to include generating block select signals from the most significant address bits. The ordinary artisan would have been motivated to modify Nagata in the above manner for the purpose of reducing the delay time that results from a high "fan-out" of the multiplexes and decoder circuits on the respective hierarchy level (Schmitt-Landsiedel Col. 7, ll. 5-17).
Regarding claim 13, Nagata as modified by Park, Ashmore, and Schmitt-Landsiedel teaches the limitations of claim 12.
Nagata together with Park further teaches the step of initializing the memory blocks in sequence accordingly comprises:
when the read write selection signal is at a first logic level (Park’s
W
E
¯
is asserted low for a write – see Col. 2, ll. 1-9)), and the set signal is at a second logic level (Nagata’s RESET signal is asserted high – see FIG. 6), conducting a set operation to write preset data (¶[0002] of the present application gives examples of preset data as 00h and FFh) into all the storage units in the target memory block within one cycle time (Nagata ¶[0029] teaches “When the first bit line BT is set to the write data of the high level ‘1’ and the second bit line BB is set to the write data of the low level ‘0’ and the word line WL is set to the selected level of the high level, the transfer transistors N3 and N4 are turned on and the data of the high level ‘1’ is stored in the memory cell MC,” which results in “preset data” FFh written to the block. This is done by driving the bit lines to their respective levels with buffers WBT and WBB – see FIGS. 1 and 3 and ¶[0054].) within one cycle time (Nagata FIG. 6 shows the RESET initialization operation occurs in one one-shot clock cycle on the CLK line; ¶[0055]).
Regarding claim 14, Nagata as modified by Park, Ashmore, and Schmitt-Landsiedel teaches the limitations of claim 12.
Nagata further teaches receiving input data (FIG. 3; ¶[0041] teaches “The write buffer/sense amplifier unit WSP includes a data input circuit DIN to which input data Din to be written to a memory cell selected at the time of normal writing is supplied”); and
when the read write selection signal and the set signal are at a first logic level (Both Park’s
W
E
¯
and Nagata’s RESET are low), conducting a write operation to write the input data into the corresponding storage unit in the target memory block (¶[0045] teaches reset state is only entered when RESET is high, so normal operating modes including read and write modes may be used when RESET is low; a normal write is done per ¶[0041], which teaches “The data input circuit DIN generates write data DT to the bit line BT and write data DB to the bit line BB based on the input data Din during normal writing. The data DT and BT are supplied to the bit lines BT and BB via the write column switches…”).
Regarding claim 15, Nagata as modified by Park, Ashmore, and Schmitt-Landsiedel teaches the limitations of claim 14.
Nagata together with Park further teaches the step of initializing the memory blocks in sequence accordingly comprises:
when the read write selection signal is at the first logic level (Park’s
W
E
¯
is asserted low for a write – see Col. 2, ll. 1-9)), and the set signal is at a second logic level (Nagata’s RESET signal is asserted high – see FIG. 6), conducting a set operation to write the preset data (see claim objections) into all the storage units in the target memory block (Nagata ¶[0029] teaches “When the first bit line BT is set to the write data of the high level ‘1’ and the second bit line BB is set to the write data of the low level ‘0’ and the word line WL is set to the selected level of the high level, the transfer transistors N3 and N4 are turned on and the data of the high level ‘1’ is stored in the memory cell MC,” which results in “preset data” FFh written to the block. This is done by driving the bit lines to their respective levels with buffers WBT and WBB – see FIGS. 1 and 3 and ¶[0054].) within one cycle time (Nagata FIG. 6 shows the RESET initialization operation occurs in one one-shot clock cycle on the CLK line; ¶[0055]).
Regarding claim 16, Nagata as modified by Park, Ashmore, and Schmitt-Landsiedel teaches the limitations of claim 14.
Park further teaches when the read write selection signal is at a second logic level (
W
E
¯
is set high for a read), conducting a read operation (Col. 1, ll. 56-64 teach “When external write enable signal WE is `H` (i.e., logical `1`)…a burst read cycle begins”) to read data stored in the corresponding storage unit in the target memory block, and outputting the read data as output data (FIG. 5 shows data from memory cell 300 may be sensed by SSA1 and stored by output buffer SRL1 – see also FIGS. 2-4).
12. Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata (US 20220199153 A1) in view of Park, et al (US 6031785 A), hereinafter Park, further in view of Ashmore, Jr. (US 5267204 A), hereinafter Ashmore, further in view of Suzuki (US 5748558 A), and further in view of Cline, et al (US 4528666 A), hereinafter Cline.
Regarding claim 17, Nagata as modified by Park and Ashmore teaches the limitations of claim 11.
Nagata further teaches receiving a clock signal (FIG. 5, CLK) and a chip enable signal (FIG. 5, RS).
Nagata does not teach the method responds to the clock signal to capture logic levels of the read write selection signal, the set signal and the chip enable signal.
Suzuki teaches the method responds to the clock signal to capture logic levels of the read write selection signal and the chip enable signal (FIG. 1, registers 102, 103 clocked by clock signal K; Col. 1, ll. 15-20 teach “An address signal supplied from the external is stored in the address register 101 in synchronous with a clock signal K generated internally based on an external clock signal. Similarly, the SRAM comprises registers 102 and 103 for holding a chip select signal /S and a write signal /W respectively.”)).
Cline teaches the method responds to the clock signal to capture the set signal (FIG. 2; Col. 9, ll. 20-21).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Suzuki into the method of Nagata to include registers for synchronously capturing exterior control signals. The ordinary artisan would have been motivated to modify Nagata in the above manner for the purpose of generating a plurality of internal control signals based on the external control signals (Suzuki Col. 5, ll. 48-59).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Cline into the method of Nagata to include a reset flip-flop circuit clocked by an external clock. The ordinary artisan would have been motivated to modify Nagata in the above manner for the purpose of generating a synchronous reset signal from an asynchronous reset signal (Cline Col. 9, ll. 9-21).
Regarding claim 18, Nagata as modified by Park, Ashmore, Suzuki, and Cline teaches the limitations of claim 17.
Nagata further teaches when the chip enable signal is at a second logic level (FIG. 7, RS is high), the semiconductor memory apparatus is in an idle state (¶[0048]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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