DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 6-12 have been withdrawn.
Claims 1-5 and 13-23 have been examined.
Election/Restrictions
Claims 6-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a non-elected invention. Election was made without traverse in the response filed July 1, 2026.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(a)-(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application claims priority to a number of U.S. Provisional Applications, the earliest of which was filed on February 16, 2024.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statement dated April 27, 2025 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. A copy of the PTOL-1449 initialed and dated by the Examiner is attached to the instant office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 and 13-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites, at lines 3-5, “each compute slice…is coupled to a successor compute slice and a predecessor compute slice by a barrier register set.” This language contradicts the written description and introduces uncertainty as to the scope of the claims. The written description does not show a single barrier register set coupling a given compute slice to both a predecessor and successor. Instead, the written description shows one barrier register coupling the compute slice to a predecessor and a second barrier register set coupling the compute slice to its successor. See, e.g., Figure 3, e.g., 320, 330, and 340, and related description. For purposes of examination, the claim is interpreted as being consistent with Figure 3. Claims 22 and 23 include similar language and are similarly rejected.
Figure 1 recites “allocating a first slice task…to” and “allotting a second slice task…to.” It cannot be determined with sufficient certainty what difference in scope is encompassed by the use of “allocating” versus “allotting.” For purposes of examination, both terms are interpreted as being synonymous with assigning. Claims 22 and 23 include similar language and are similarly rejected.
Claim 18 recites, “speculatively executing the second compute slice.” This language introduces ambiguity as to the scope of the claims. The second compute slice is hardware, and the meaning of speculatively executing hardware cannot be definitely determined. For purposes of examination the limitation is interpreted as, “speculatively executing the second slice task.”
Claims 2-5 and 13-21 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 13, 14, 18, 19, 22, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Non-Patent Literature “Multiscalar Processors,” by Sohi et al. (hereinafter referred to as “Sohi”).
Regarding claims 1, 22, and 23, Sohi discloses:
a processor-implemented method for compiling comprising: accessing a processing unit comprising a plurality of compute slices, a plurality of barrier register sets, a control unit, and a memory system, wherein each compute slice within the plurality of compute slices includes at least one execution unit, is known to a compiler, and is coupled to a successor compute slice and a predecessor compute slice by a barrier register set in the plurality of barrier register sets, wherein the barrier register set provides for communication of data between successive compute slices (Sohi discloses, at § 2.1, a processor that has a collection of processing units that execute instructions, i.e., compute slices. As described at the abstract, each processing unit includes a copy of a register file, i.e., barrier register set, that is used to route results between adjacent processing units with help of a compiler, which discloses the processing units are known to a compiler.);
evaluating, by the compiler, a compiled program, wherein the compiled program includes a plurality of basic blocks, wherein the evaluating is based on a control flow graph (CFG) (Sohi discloses, at § 1, the compiler evaluates a program’s CFG, which includes basic blocks.);
creating, by the compiler, a first hyperblock, wherein the first hyperblock includes at least two basic blocks within the plurality of basic blocks that were evaluated, and wherein the creating includes replacing one or more branch instructions with one or more skip instructions, wherein the one or more skip instructions direct instruction execution between the at least two basic blocks in the first hyperblock (Sohi discloses at § 2.1, the compiler divides the CFG into tasks that correspond to multiple basic blocks, which discloses creating a hyperblock. Sohi discloses, at Figure 4, a task (hyperblock) that includes branches within the task that skip over basic blocks, e.g., bne…OUTER directs instruction of the basic blocks in the task. This intra-task branch discloses a skip instruction.);
allocating a first slice task, by the control unit, to a first compute slice in the plurality of compute slices, wherein the first slice task comprises the first hyperblock that was created by the compiler (Sohi discloses, at § 2.1, a sequencer, i.e., control unit, assigns tasks to processing units, which discloses allocating a first slice task, by the control unit, to a first compute slice in the plurality of compute slices, wherein the first slice task comprises the first hyperblock that was created by the compiler.);
allotting a second slice task, by the control unit, to a second compute slice in the plurality of compute slices, wherein the second slice task comprises at least one basic block within the plurality of basic blocks, wherein the allotting is based on branch prediction logic within the control unit, and wherein the second compute slice is coupled to the first compute slice by a first barrier register set in the plurality of barrier register sets (Sohi discloses, at § 2.1, a sequencer, i.e., control unit, assigns tasks to processing units, which discloses allotting a second slice task, by the control unit, to a second compute slice in the plurality of compute slices, wherein the second slice task comprises at least one basic block within the plurality of basic blocks. As disclosed at § 2.2, assignment is based on branch prediction.);
initializing pointers, wherein a head pointer points to the first compute slice, and wherein a tail pointer points to the second compute slice (Sohi discloses, at § 2.2, head and tail pointers, which discloses initializing and pointing to first and second units.); and
executing the compiled program, wherein the executing begins at the first compute slice (Sohi discloses, at § 2.2, executing starting with a first unit.).
Regarding claim 2, Sohi, discloses the elements of claim 1, as discussed above. Sohi also discloses:
a first skip instruction within the one or more skip instructions includes a conditional operation Sohi discloses, at Figure 4, a task (hyperblock) that includes conditional branches.).
Regarding claim 3, Sohi, discloses the elements of claim 2, as discussed above. Sohi also discloses:
the first hyperblock is executed, by the first compute slice, without a prediction of the conditional operation (Sohi discloses, at § 4.1, internal branches need not be predicted.).
Regarding claim 13, Sohi, discloses the elements of claim 1, as discussed above. Sohi also discloses:
the creating includes a second hyperblock (Sohi discloses at § 2.1, the compiler divides the CFG into tasks that correspond to multiple basic blocks, which discloses creating a second hyperblock.).
Regarding claim 14, Sohi, discloses the elements of claim 13, as discussed above. Sohi also discloses:
the second slice task comprises the second hyperblock (Sohi discloses, at Figure 4, tasks include multiple blocks, which discloses the second slice task comprises the second hyperblock.).
Regarding claim 18, Sohi, discloses the elements of claim 1, as discussed above. Sohi also discloses:
the executing includes speculatively executing the second compute slice (Sohi discloses, at § 2.1, speculative execution of tasks.).
Regarding claim 19, Sohi, discloses the elements of claim 1, as discussed above. Sohi also discloses:
the one or more skip instructions comprise a forward branch within the first hyperblock (Sohi discloses, at Figure 4, forward branches within the task.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Sohi.
Regarding claim 4, Sohi, discloses the elements of claim 2, as discussed above. Sohi also discloses:
… branch prediction hardware (Sohi discloses, at § 4.1, branch prediction hardware.).
Sohi does not explicitly disclose the aforementioned branch prediction hardware is included in the first compute slice. However, it would have been obvious to include the branch prediction hardware in the first compute slice because whether to incorporate a centralized or distributed approach to branch prediction is a determination based on well-known tradeoffs. This determination is within the level of ordinary skill in the art and represents an obvious design choice based on circumstance.
Regarding claim 5, Sohi, discloses the elements of claim 4, as discussed above. Sohi also discloses:
the first hyperblock is executed, by the first compute slice, with a prediction of the conditional operation, wherein the prediction is based on the branch prediction hardware…(Sohi discloses, at § 4.1, branches that separate tasks, e.g., those in an outer loop, are predicted.).
Sohi does not explicitly disclose the aforementioned branch prediction hardware is included in the first compute slice. However, it would have been obvious to include the branch prediction hardware in the first compute slice because whether to incorporate a centralized or distributed approach to branch prediction is a determination based on well-known tradeoffs. This determination is within the level of ordinary skill in the art and represents an obvious design choice based on circumstance.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sohi in view of US Publication No. 2017/0083431 by Burger et al. (hereinafter referred to as “Burger”).
Regarding claim 15, Sohi, discloses the elements of claim 14, as discussed above. Sohi does not explicitly disclose the first hyperblock includes a first header, wherein the first header includes a number of instructions within the first hyperblock.
However, in the same field of endeavor (e.g., instruction processing) Burger discloses:
a block header that includes an indication of the instruction block size (Burger discloses, at ¶ [0070], a block header that includes an indication of the instruction block size.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sohi to include a header, as disclosed by Burger, in order to improve performance by efficiently controlling block execution. See Burger, ¶ [0070].
Regarding claim 16, Sohi, discloses the elements of claim 15, as discussed above. Sohi does not explicitly disclose the allocating includes determining, by the control unit, an end of the first hyperblock, wherein the determining is based on the number of instructions within the first hyperblock.
However, in the same field of endeavor (e.g., instruction processing) Burger discloses:
determining an end of a block based on the number of instructions in the block (Burger discloses, at ¶ [0070], determining the instruction block size based on the number of instructions, which disclose determining an end of the block.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sohi to include a header, as disclosed by Burger, in order to improve performance by efficiently controlling block execution. See Burger, ¶ [0070].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sohi in view of US Publication No. 2019/0138365 by Purnell et al. (hereinafter referred to as “Purnell”).
Regarding claim 17, Sohi, discloses the elements of claim 1, as discussed above. Sohi also discloses:
Sohi does not explicitly disclose the first hyperblock is included in an object file from the compiler.
However, in the same field of endeavor (e.g., instruction processing) Purnell discloses:
generating object files (Purnell discloses, at ¶ [0095], generating object files.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sohi to include an object file because doing so is a standard step in producing usable code.
Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sohi in view of US Publication No. 2022/0308543 by Paudel (hereinafter referred to as “Paudel”).
Regarding claim 20, Sohi, discloses the elements of claim 1, as discussed above. Sohi also discloses:
the evaluating includes identifying a sub-CFG within the CFG, wherein the sub-CFG includes an entry basic block within the plurality of basic blocks…wherein the sub-CFG includes an exit basic block within the plurality of basic blocks… (Sohi discloses, at Figure 4 and § 4.1, identifying a sub-CFG, e.g., an inner loop, that has, by definition, an entry and exit basic block.).
Sohi does not explicitly disclose the entry basic block comprises a single entry point to the sub-CFG and the exit basic block comprises a single exit point from the sub- CFG.Paudel
However, in the same field of endeavor (e.g., instruction processing) Paudel discloses:
single entry and exit points (Paudel discloses, at Figure 4, a single entry point, e.g., at 405, and a single exit point, e.g., at 430, for the sub-CFG that includes, e.g., 405, 410, and 430.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sohi to include single entry and exit points, as disclosed by Paudel, because the structure of CFGs is dependent on the nature of the program, and allowing single entry and exit points allows a greater range of programmability.
Regarding claim 21, Sohi, discloses the elements of claim 20, as discussed above. Sohi does not explicitly disclose selecting the exit basic block, wherein the exit basic block is based on a nearest common post-dominator of one or more successor basic blocks of the entry basic block, wherein the one or more successor basic blocks are within the sub-CFG.
However, in the same field of endeavor (e.g., instruction processing) Paudel discloses:
determining an exit point based on nearest common post-domination of successor blocks of the entry block (Paudel discloses, at ¶ [0042], determining the CFG based on post domination.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sohi to include determining the exit block based on post-domination to ensure correct operation of the program. See, e.g., ¶ [0060].
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 5887166 by Mallick discloses assigning tasks to thread, head and exit pointer.
US 20190287205 by Ramadoss discloses rings and compute slices.
US 5179715 by Andoh discloses buffers between PEs.
US 6993669 by Sherburn discloses buffers between processing units.
US 20030233641 by Hank discloses hyperblocks.
US 5493675 by Faiman discloses object files.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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