Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12243602 and claim 1-20 of U.S. Patent No. 11894086.
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Current Application # 19055778
US Pat # 12243602
For example:
Claim 1:
1. A control circuit, comprising: a first clock generator configured to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal; and a second clock generator configured to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal;wherein the control circuit is configured to: provide, based on a first logic state the DFTEN signal, an output clock signal that follows the DDCK signal; and provide, based on a second logic state of the DFTEN signal, the output clock signal that follows the MDCK signal.
For example:
Claim 1:
1. A control circuit, comprising: a first clock generator configured to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal; and a second clock generator configured to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal; wherein in response to the DFTEN signal being in a high logic state, an output clock signal, provided by the control circuit, follows the DDCK signal, and in response to the DFTEN signal being in a low logic state, the output clock signal follows the MDCK signal.
Even though the claims at issue are not identical but overall scope of the claims are identical and they are not patentably distinct from each other. For example, the above limitation “first logic state” and “second logic state” in current application 19055778 and the limitation “high logic state” and “low logic state” in US Pat # 12243602 (and Pat # 11894086, claim 19) are not identical but they are not patentably distinct from each other.
Claims 1-20 would be allowable if the double patenting rejection set forth in this office action is overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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