DETAILED ACTION
This action is responsive to the following communications: the Application filed February 21, 2025, and the information disclosure statement (IDS) filed March 20, 2026. This application is a CON of 18/066,306.
Claims 1-20 are pending. Claims 1, 10 and 17 are independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 20, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,260,904. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,260,904
Comment
Claim 1. A memory device comprising a plurality of columns, wherein each column of the plurality of columns of the memory device comprises:
a first plurality of memory cells;
a first pair of bit lines connected to each of the first plurality of bit cells, and
a second pair of bit lines connectable to the first pair of bit lines through a plurality of pair of switches at a first end of the second pair of bit lines and the first pair of bit lines, the first end being opposite to a second end, the second end being closer to a sense amplifier,
wherein the second pair of bit lines remain disconnected from the first pair of bit lines during a read operation in the memory device, and wherein the second pair of bit lines are connected to the first pair of bit lines during a write operation in the memory device through the plurality of switches.
Claim 1. A memory device comprising a plurality of columns,
wherein each column of the plurality of columns of the memory device comprises:
a first plurality of memory cells;
a first pair of bit lines connected to each of the first plurality of bit cells; and
a second pair of bit lines connectable to the first pair of bit
lines through a plurality of pair of switches, wherein a first pair of switches of the plurality of pair of switches is connected between the first pair of bit lines and the
second pair of bit lines, wherein a second pair of switches of the plurality of pair of switches is connected between the first pair of bit lines and the second pair of bit lines after a first predetermined number of rows of a plurality of rows of a cell array of the memory
device from the first pair of switches, wherein the plurality of pair of switches remain switched off thereby disconnecting the second pair of bit lines from the first pair of bit lines during a read operation in the memory device, and wherein the plurality of pair of
switches are switched on thereby connecting the second pair of bit lines to the first pair of bit lines during a write operation in the memory device through the plurality of pair of switches.
Note footnote1
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-10, 14-17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yabe (US 2005/0207242).
Regarding independent claims 1, 10 and 17, e.g., FIG. 2 and/or FIG. 5 along with FIG. 4 of Yabe discloses a memory device comprising a plurality of columns, wherein each column of the plurality of columns of the memory device comprises:
a first plurality of memory cells (e.g., FIG. 2: M0, … M15);
a first pair of bit lines (e.g., BL1-0 and BL1-0B …) connected to each of the first plurality of bit cells, and
a second pair of bit lines (GBL and GBLB) connectable to the first pair of bit lines (BL1-0 and BL1-0B) through a plurality of pair of switches (see two transistors (same as NM1 and NM2) in Sub-array <1>) at a first end (top end) of the second pair of bit lines and the first pair of bit lines, the first end being opposite to a second end, the second end (bottom end) being closer to a sense amplifier (104 I/O circuit2), wherein the second pair of bit lines remain disconnected from the first pair of bit lines during a read operation in the memory device (NM1-2 turned “OFF” by WEB; see e.g., para. 0045: … a write enable signal WEB … the write transfer gates NM1 and NM2 …), and wherein the second pair of bit lines are connected to the first pair of bit lines during a write operation in the memory device through the plurality of switches (NM1-2 turned “ON” by WEB) (see e.g., FIGS. 2-5 and accompanying disclosure)
Further, regarding method claim 173, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
Regarding claim 2, which depends from claim 1, Yabe discloses the first pair of bit lines comprises a first bit line and a first complementary bit line, wherein the second pair of bit lines comprises a second bit line and a second complementary bit line, wherein the first bit line is connectable to the second bit line, and wherein the first complementary bit line is connectable to the second complementary bit line (see e.g., FIG. 2 and accompanying disclosure).
Regarding claim 3, which depends from claim 1, Yabe discloses one pair of switches of the plurality of pair of switches are connected between the first pair of bit lines and the second pair of bit lines after each predetermined number of rows (see e.g., FIG. 2 and accompanying disclosure, i.e., 16 Row).
Regarding claims 4 and 16, which depends from claims 1 and 10, respectively, Yabe discloses each pair of switches in a row are connected to a write enable line and switched on through the write enable line (see e.g., FIG. 2 and accompanying disclosure).
Regarding claims 8, 14 and 20, which depends from claims 1, 10 and 17, respectively, Yabe discloses an equalizer switch, wherein the first pair of bit lines comprises a first bit line and a first complementary bit line, and wherein the equalizer switch selectively connects the first bit line with the first complementary bit line (see e.g., FIG. 2 and accompanying disclosure, i.e., EQB in Row decoder<0>, <1>, …).
Regarding claims 9 and 15, which depends from claims 1 and 14, respectively, Yabe discloses the first pair of bit lines comprises a first bit line and a first complementary bit line, and wherein the first bit line is selectively connectable with the first complementary bit line with an equalizer switch, and wherein the equalizer switch is provided for every predetermined number of rows (see e.g., FIG. 2 and accompanying disclosure, i.e., EQB in Row decoder<0>, <1>, …, placed every 16 Rows).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7, 12-13 and 18-19 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yabe (US 2005/0207242) in view of e.g., Shau (US 2001/0010654).
Regarding claims 5-7, 12-13 and 18-19, Yabe teaches the limitations applied to claims 1, 10 and 17, respectively.
Yabe is silent with respect to the first pair of bit lines are formed in a first metal layer and the second pair of bit lines are formed in a second metal layer, wherein the second metal layer is different from the first metal layer; the first pair of bit lines are formed in a first metal layer and the second pair of bit lines are formed in a second metal layer, wherein the second metal layer is a higher metal layer than the first metal layer; and the second metal layer is at least two layer higher than the first metal layer.
However, local bit line pair (claimed the first pair of bit line) and global bit line pair (claimed the second pair of bit line) routed in parallel are formed in a metal layer, whether single metal layer or double metal layer, is a well-known technology for a type of memory layout for its purpose.
For support, of the above asserted facts, see for example, Shau (US 2001/0010654), paragraph [0068]: … In this example, the memory unit has two levels of bit lines--the unit level bit lines … and the block level bit lines … The block bit lines are made by the first layer metal (metal 1), … The unit bit lines are made by the second layer metal (metal 2); Proebsting (US 6,356,485), col. 48, lines 65-67, line The global input pair GIN, GINB corresponding to the given group of bit lines, and which pair is preferably implemented in the top layer of metal and runs …
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize metal layers in bit lines routing because these conventional technology are well established in the art of the memory devices.
Claim 11 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Yabe (US 2005/0207242) in view of Song et al. (US 2012/0206988).
Regarding claim 11, Yabe teaches the limitations applied to claim 10.
Yabe is silent with respect to a negative voltage generator, wherein the negative voltage generator, when enabled, is operative to provide a negative voltage to the first pair of bit lines and the second pair of bit lines.
Song et al. disclose the deficiencies in FIGS 1-2 and accompanying disclosure, e.g., para. 0077: … Accordingly, the negative voltage VNEG is provided to a memory cell 211 … through the first local bitline LBL1, …, i.e., local bit line pair (claimed the first pair of bit lines) and global bit line pair (claimed the second pair of bit lines) are provided a negative voltages as claimed.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Song et al. to the teaching of Yabe such that a memory device, as taught by Yabe, utilizes a negative voltage to bit line pairs, as taught by Song et al., for the purpose of booting bit line voltage, thereby assisting write ability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 10 and 17, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
2 An input/output (I/O) circuit comprising a sense amplifier that performs a data output operation is an inherent characteristic of memory.
3 See Yabe’s pre-charge operation in e.g., FIG. 2 and accompanying disclosure, e.g., para. 0045.
Prosecution Insights