Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the preliminary amendment received 05/23/2025.
Claim 9 is amended.
Claim 1 – 20 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 120 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/24/2025 was received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting over claims 1 – 20 of U.S. Patent No. 12,259,783 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/061051
Claim 1 – Patent 12,259,783
A semiconductor device, comprising:
A semiconductor device, comprising:
an error correction code circuit configured to generate first data according to second data;
an error correction code circuit configured to generate first data according to second data;
a write circuit;
a write circuit configured
a register circuit configured to generate a reset enable signal according to the first data and the second data for a reset operation to a memory cell by the write circuit; and
a register circuit configured to generate reset information and a reset enable signal according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data;
a first logic circuit configured to generate a reset command according to the reset enable signal and a write signal,
a first logic circuit configured to generate a reset command according to the reset enable signal and a write signal; and
wherein the write circuit is configured to be controlled by the reset command to continue performing a write operation when the reset enable signal has a logic state indicating performing the reset operation to the memory cell.
[a write circuit configured] to be controlled by the reset command to continue performing a write operation to the memory cell when the reset enable signal has a logic state indicating activation of performing a reset operation to the memory cell by the write circuit.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/061051is an obvious variation of the claimed subject matter of independent claim 1, of patent 12,259,783. Specifically, both claim 1, of the current application 19/061051, and claim 1, of patent 12,259,783 discloses: A semiconductor device, comprising: “an error correction code circuit configured to generate first data according to second data”, “a write circuit”, “a register circuit”, and “a first logic circuit”.
One of ordinary skill in the art would recognize the semiconductor device disclosed by claim 1, of the current application 19/061051, as a broad recitation of the operations performed by the semiconductor device disclosed in claim 1 of Patent 12,259,783. A semiconductor device performing the operations and a semiconductor device capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the semiconductor device claim 1, of the current application 19/061051, as performing the operations of the apparatus of claim 1, of U.S. Patent 12,259,783, and as such are obvious variants of each other.
Claim 2 – Application 19/061051
Claim 2 – Patent 12,259,783
Claim 3 – Application 19/061051
Claim 3 – Patent 12,259,783
Claim 4 – Application 19/061051
Claim 4 – Patent 12,259,783
Claim 5 – Application 19/061051
Claim 5 – Patent 12,259,783
Claim 6 – Application 19/061051
Claim 6 – Patent 12,259,783
Claim 7 – Application 19/061051
Claim 7 – Patent 12,259,783
Claim 8 – Application 19/061051
Claim 8 – Patent 12,259,783
Claim 9 – Application 19/061051
Claim 9 – Patent 12,259,783
Claim 10 – Application 19/061051
Claim 10 – Patent 12,259,783
Claim 11 – Application 19/061051
Claim 11 – Patent 12,259,783
Claim 12 – Application 19/061051
Claim 12 – Patent 12,259,783
Claim 13 – Application 19/061051
Claim 13 – Patent 12,259,783
Claim 14 – Application 19/061051
Claim 14 – Patent 12,259,783
Claim 15 – Application 19/061051
Claim 15 – Patent 12,259,783
Claim 16 – Application 19/061051
Claim 16 – Patent 12,259,783
Claim 17 – Application 19/061051
Claim 17 – Patent 12,259,783
Claim 18 – Application 19/061051
Claim 18 – Patent 12,259,783
Claim 19 – Application 19/061051
Claim 19 – Patent 12,259,783
Claim 20 – Application 19/061051
Claim 20 – Patent 12,259,783
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting over claims 1 – 20 of U.S. Patent No. 11,609,815 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/061051
Claim 1 – Patent 11,609,815
A semiconductor device, comprising:
A semiconductor device, comprising:
a memory circuit configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit;
an error correction code circuit configured to generate first data according to second data;
an error correction code circuit configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data;
a write circuit;
a write circuit configured
a register circuit configured to generate a reset enable signal according to the first data and the second data for a reset operation to a memory cell by the write circuit; and
a register circuit configured to output, based on the error information,
a first logic circuit configured to generate a reset command according to the reset enable signal and a write signal,
reset information corresponding to the at least one address signal; and
wherein the write circuit is configured to be controlled by the reset command to continue performing a write operation when the reset enable signal has a logic state indicating performing the reset operation to the memory cell.
[a write circuit configured] to reset the at least one memory cell according to the reset information.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/061051is an obvious variation of the claimed subject matter of independent claim 1, of patent 11,609,815. Specifically, both claim 1, of the current application 19/061051, and claim 1, of patent 11,609,815 discloses: A semiconductor device, comprising: “an error correction code circuit configured to generate first data according to second data”, “a write circuit”, and “a register circuit”.
One of ordinary skill in the art would recognize the semiconductor device disclosed by claim 1, of the current application 19/061051, as a broad recitation of the operations performed by the semiconductor device disclosed in claim 1 of Patent 11,609,815. A semiconductor device performing the operations and a semiconductor device capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the semiconductor device claim 1, of the current application 19/061051, as performing the operations of the apparatus of claim 1, of U.S. Patent 11,609,815, and as such are obvious variants of each other.
Claim 2 – Application 19/061051
Claim 1 – Patent 11,609,815
Claim 3 – Application 19/061051
Claim 3 – Patent 11,609,815
Claim 4 – Application 19/061051
Claim 4 – Patent 11,609,815
Claim 5 – Application 19/061051
Claim 5/6 – Patent 11,609,815
Claim 6 – Application 19/061051
Claim 7 – Patent 11,609,815
Claim 7 – Application 19/061051
Claim 8 – Patent 11,609,815
Claim 8 – Application 19/061051
Claim 9 – Patent 11,609,815
Claim 9 – Application 19/061051
Claim 10 – Patent 11,609,815
Claim 10 – Application 19/061051
Claim 10 – Patent 11,609,815
Claim 11 – Application 19/061051
Claim 10 – Patent 11,609,815
Claim 12 – Application 19/061051
Claim 10/11 – Patent 11,609,815
Claim 13 – Application 19/061051
Claim 12 – Patent 11,609,815
Claim 14 – Application 19/061051
Claim 14 – Patent 11,609,815
Claim 15 – Application 19/061051
Claim 1 – Patent 11,609,815
Claim 16 – Application 19/061051
Claim 7/8 – Patent 11,609,815
Claim 17 – Application 19/061051
Claim 5– Patent 11,609,815
Claim 18 – Application 19/061051
Claim 3 – Patent 11,609,815
Claim 19 – Application 19/061051
Claim 9 – Patent 11,609,815
Claim 20 – Application 19/061051
Claim 4 – Patent 11,609,815
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
CHUNG; Hoi-Ju et al. US 20170031756 A1
TODA; Haruki US 20100235714 A1
Philipp; Jan Boris et al. US 20100002498 A1
a register circuit configured to generate a reset enable signal according to the first data and the second data for a reset operation to a memory cell by the write circuit; and
a first logic circuit configured to generate a reset command according to the reset enable signal and a write signal,
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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