DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4-8, 10, 11 and 14-20 of U.S. Patent No. 11,568,948. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-9 and 11-20 are anticipated by claims 1, 2, 4-8, 10, 11 and 14-20 of the patent and claim 10 would have been obvious over claim 2 of the patent.
Regarding claim 1, claim 1 of the patent recites a memory circuit, comprising:
a non-volatile memory cell (claim 1, line 2);
a comparator coupled to the non-volatile memory cell, and configured to generate a first output signal, the comparator comprising a first input terminal and a first output terminal, the first input terminal being coupled to the non-volatile memory cell by a first node, and being configured to receive a first voltage, the first output terminal being configured to output the first output signal; and
a detection circuit coupled to the comparator and the non-volatile memory cell, the detection circuit configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the detection circuit, the detection circuit comprising:
a flip-flop comprising a first input terminal of the flip-flop coupled to the first output terminal of the comparator, a second input terminal of the flip-flop configured to receive a first data signal, a third input terminal of the flip-flop configured to receive a first reset signal, a first output terminal of the flip-flop configured to generate a second output signal, and a second output terminal of the flip-flop configured to generate an inverted second output signal (claim 1, lines 6-28).
Regarding claim 2, claim 4 of the patent recites the memory circuit of claim 1, wherein the detection circuit further comprises:
a first transistor comprising a first gate, a first drain, and a first source, wherein the first gate of the first transistor is coupled to the second output terminal of the flip-flop and configured to receive the inverted second output signal, the first source of the first transistor is coupled to a second node, and the first drain of the first transistor is coupled to the first node, the first input terminal of the comparator and the non-volatile memory cell,
wherein the second output signal corresponds to data stored in the non-volatile memory cell.
Regarding claim 3, claim 5 of the patent recites the memory circuit of claim 2, further comprising:
a first current source having a first end and a second end, the first end of the first current source being coupled to the second node and the first source of the first transistor, and the second end of the first current source being coupled to a reference voltage supply.
Regarding claim 4, claim 6 of the patent recites the memory circuit of claim 3, wherein the detection circuit further comprises:
a second transistor comprising a second gate, a second drain, and a second source, wherein the second gate of the second transistor is coupled to the first gate of the first transistor and the second output terminal of the flip-flop, and the second gate of the second transistor is configured to receive the inverted second output signal, the second source of the second transistor is coupled to a second voltage supply different from the reference voltage supply, and the second drain of the second transistor is coupled to the first node, the first input terminal of the comparator and the non-volatile memory cell.
Regarding claim 5, claims 4 and claim 6 of the patent recite the memory circuit of claim 4, wherein the second drain of the second transistor is further coupled to the first drain of the first transistor (both of the drains of the first transistor and the second transistors are connected to the first node).
Regarding claim 6, claim 7 of the patent recites the memory circuit of claim 4, wherein the first transistor is a first transistor type.
Regarding claim 7, claim 8 of the patent recites the memory circuit of claim 6, wherein the second transistor is a second transistor type different from the first transistor type.
Regarding claim 8, claim 10 of the patent recites the memory circuit of claim 1, wherein the first input terminal of the comparator is a non-inverting input terminal.
Regarding claim 9, claim 2 of the patent recites the memory circuit of claim 1, wherein the non-volatile memory cell comprises:
a first transistor comprising a first gate, a first drain, and a first source, wherein the first gate is coupled to a program word line; and
a second transistor comprising a second gate, a second drain, and a second source, wherein the second gate is coupled to a read word line, the second drain is coupled to the first source, and the second source is coupled to the first node and the first input terminal of the comparator.
Regarding claim 10, it would have been obvious to one of ordinary skill in the art to recognize the memory circuit of claim 10 and the memory circuit of claim 2 of the patent are identical in structure; therefore, the first transistor is a first transistor type; and the second transistor is the first transistor type .
Regarding claim 11, claim 11 of the patent recites a memory circuit, comprising:
a first non-volatile memory cell configured to store a first value;
a second non-volatile memory cell configured to store a second value inverted from the first value;
a first sense amplifier coupled to the first non-volatile memory cell, and configured to generate a first output signal, the first sense amplifier comprises:
a first comparator comprising a first input terminal and a first output terminal, the first input terminal of the first comparator being coupled to the first non-volatile memory cell by a first node, and being configured to receive a first voltage, and the first output terminal of the first comparator being configured to output the first output signal;
a first detection circuit coupled to the first sense amplifier and the first non-volatile memory cell, the first detection circuit configured to latch the first output signal and disrupt a first current path between the first non-volatile memory cell and the first sense amplifier, the first detection circuit comprising:
a first inverter coupled to the first comparator, and configured to generate an inverted first output signal in response to the first output signal; and
a first transistor coupled to the first inverter, the first node, the first input terminal of the first comparator and the first non-volatile memory cell; and
a second sense amplifier coupled to the second non-volatile memory cell, and configured to generate a second output signal.
Regarding claim 12, claim 14 of the patent recites the memory circuit of claim 11, wherein the first sense amplifier further comprises:
a first current source having a first end and a second end, the first end of the first current source being coupled to the first node, the first input terminal of the first comparator, the first transistor and the first non-volatile memory cell, and the second end of the first current source being coupled to a reference voltage supply.
Regarding claim 13, claim 15 of the patent recites the memory circuit of claim 12, wherein the second sense amplifier comprises:
a second comparator comprising a first input terminal of the second comparator and a first output terminal of the second comparator, the first input terminal of the second comparator being coupled to the second non-volatile memory cell by a second node, and being configured to receive a second voltage, and the first output terminal of the second comparator being configured to output the second output signal.
Regarding claim 14, claim 15 of the patent recites the memory circuit of claim 13, wherein the second sense amplifier further comprises:
a second current source having a first end and a second end, the first end of the second current source being coupled to the second node, the first input terminal of the second comparator and the second non-volatile memory cell, and the second end of the second current source being coupled to the reference voltage supply.
Regarding claim 15, claim 16 of the patent recites the memory circuit of claim 14, further comprising:
a second detection circuit coupled to the second sense amplifier and the second non-volatile memory cell, the second detection circuit configured to latch the second output signal and disrupt a second current path between the second non-volatile memory cell and the second sense amplifier.
Regarding claim 16, claim 17 of the patent recites the memory circuit of claim 15, wherein the second detection circuit comprises:
a second inverter coupled to the second comparator, and configured to generate an inverted second output signal in response to the second output signal.
Regarding claim 17, claim 17 of the patent recites the memory circuit of claim 16, wherein the second detection circuit further comprises:
a second transistor coupled to the second inverter, the second node, the first input terminal of the second comparator and the second non-volatile memory cell.
Regarding claim 18, claim 18 of the patent recites the memory circuit of claim 17, wherein
the first transistor is a first n-type transistor; and
the second transistor is a second n-type transistor.
Regarding claim 19, claim 19 of the patent recites the memory circuit of claim 18, wherein
the first input terminal of the first comparator is a first non-inverting input terminal, and
the first input terminal of the second comparator is a second non-inverting input terminal.
Regarding claim 20, claim 20 of the patent recites a method of operating a memory circuit, comprising:
turning on a select transistor in response to a select signal, the select transistor being coupled between a first memory cell and a first node;
applying a first voltage to a first word line of the first memory cell thereby causing a first cell current to flow through the first memory cell to at least the first node;
comparing, by a comparator, a second voltage of the first node with a reference voltage thereby generating a first output signal;
enabling a detection circuit in response to the first output signal; and
disrupting a first current path between the select transistor and at least the first node or a second node in response to the enabling of the detection circuit, wherein disrupting the first current path between the select transistor and at least the first node or the second node comprises:
generating, by an inverter, an inverted first output signal;
turning on a first transistor in response to the inverted first output signal, the first transistor being coupled to the first node;
pulling the second voltage of the first node to the first voltage in response to the first transistor turning on; and
turning off the select transistor in response to pulling the second voltage of the first node to the first voltage.
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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