DETAILED ACTION
This Non-final action is responsive to the following communications: application filed on 02/26/2025.
Claims 1-20 are pending. Claims 1, 13, and 18 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic CON priority details.
Information Disclosure Statement
5. The information disclosure statement filed 02/26/2025 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each non-patent literature publication, foreign patents or that portion which caused it to be listed (see non-patent literature document cite no. a8-a12 copies are missing). Therefore, these references have not been considered. The remainder of the references was considered by Examiner. See MPEP § 609.05(a).
Drawings
6. Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Official notice is taken regarding the fact that Figure 1 and disclosure is prior art and commonly known to ordinary skill in the art.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
7. The disclosure is objected to because of the following informalities :
Applicant’s specification paragraphs 0021-0027 describe details of typical, conventional sram device. Furthermore, paragraphs 0021-0027 describe details of the drawing figure 1. As described above, Figure 1 should be designated as --Prior Art--. Therefore, paragraphs 0021-0027, and the other descriptions of prior art and problems, should be under the Background of the Invention section of Applicant’s Specification because the description of the related art or other information disclosed known to the applicant belongs in the Background of the Invention section, see MPEP 608.01(c) (the Specification’s Background is for description of the state of the prior art or other information known to applicant and problems involved in the prior art or other information which are solved by applicant’s invention.”).
Applicant is reminded of helpful scenario 7 explained in MPEP 2004 and encouraged to take care to see that prior art or other information cited in a specification or in an information disclosure statements is properly described and that the information is not incorrectly or incompletely characterized.
Appropriate correction is required.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1-8, 10-13, and 15-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujiwara-5671 et al. (US 2019/0385671 A1).
Regarding independent claim 1, Fujiwara-5671 teaches a memory array (Fig. 1B: 100. See para [0020] - para [0021]) comprising:
a plurality of memory cells (Fig. 1B: MC “memory cells”) distributed across a plurality of columns and a plurality of rows (Fig. 1B in context of para [0025], para [0026]);
a plurality of bit line pairs (Fig. 1B: BLs and BLBs) associated with the plurality of columns (see Fig. 1B: column 0, column 1); and
a plurality of word lines (Fig. 1B: 114s, 118s) associated with the plurality of rows (Fig. 1B: four rows),
wherein each of the plurality of memory cells (see e.g. Fig. 1B: MC in 102 in column 0) is operatively coupled to a corresponding one of the plurality of word lines (Fig. 1B: 114) and a corresponding one of the plurality of bit line pairs (Fig. 1B: BL_TOP(0), BLB_TOP(0)),
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wherein first memory cells (Fig. 1B: MCs 130A in column 0 in 102) of the plurality of memory cells (Fig. 1B) are operatively coupled to a first bit line pair of the plurality of bit line pairs (Fig. 1B: BL_TOP[0], BLB_TOP[0]), and
second memory cells (Fig. 1B: MCs 130B in column 0 in 104) of the plurality of memory cells (Fig. 1B) are operatively coupled to a second bit line pair of the plurality of bit line pairs (Fig. 1B: BL_BOT[0], BLB_BOT[0]), and
wherein the first (Fig. 1B: MCs 130A) and second memory cells (Fig. 1B: MCs 130B) are in one of the plurality of columns (Fig. 1B: one column, column 0. See para [0027]-para [0028]).
Regarding claim 2, Fujiwara-5671 teaches the memory array of claim 1, wherein the plurality of rows comprise four rows (Fig. 1B: comprises four rows) and wherein the plurality of columns comprise four columns (Fig. 1B in context of para [0023]: comprises four columns).
Regarding claim 3, Fujiwara-5671 teaches the memory array of claim 1, wherein each of the plurality of memory cells comprises at least a first transistor (Fig. 1B: 144 with 116A. Access transistor of 6T SRAM cell) and a second transistor (Fig. 1B: 144 with 116B. Access transistor of 6T SRAM cell).
Regarding claim 4, Fujiwara-5671 teaches the memory array of claim 3, wherein gates of the first and second transistors are coupled to a corresponding word line (Fig. 1B: 144s coupled to 114 word line),
a source/drain contact of the first transistor (Fig. 1B: 144 with 116A) is coupled to a first bit line of a corresponding bit line pair (Fig. 1B: 116A. see BL_TOP), and
a source/drain contact of the second transistor (Fig. 1B: 144 with 116B) is coupled to a second bit line of the corresponding bit line pair (Fig. 1B: 116A. see BLB_TOP).
Regarding claim 5, Fujiwara-5671 teaches the memory array of claim 4, wherein the source/drain contacts of the first and second transistors continuously extend across the plurality of memory cells along a corresponding column (Fig. 1B: source/drain contacts of 144s are connected to another cell. See 130As column 0 are connected together via source/ drain contacts of access transistors)
Regarding claim 6, Fujiwara-5671 teaches the memory array of claim 4, wherein the gates of the first and second transistors continuously extending across the plurality of memory cells along a corresponding row (See Fig. 1B: 114 continuously extending across the plurality of memory cells along a corresponding row).
Regarding claim 7, Fujiwara-5671 teaches the memory array of claim 1, wherein each memory cell corresponds to one of a plurality of sub-blocks of a block (Fig. 1B: 102 top segment and 104 bottom segment).
Regarding claim 8, Fujiwara-5671 teaches the memory array of claim 7, wherein the block is one of four blocks abutted to each other along a lateral direction, each of the four blocks comprising four sub-blocks (Fig. 1B in context of para [0018]: disclosed control blocks can be configured to achieve the claimed structure).
Regarding claim 10, Fujiwara-5671 teaches the memory array of claim 1, wherein:
the first memory cells (Fig. 1B: MCs 130A in column 0 in 102) comprise a first memory cell and a second memory cell (Fig. 1B: 130As) coupled to the first bit line pair within a first column (Fig. 1B: BL_TOP[0], BLB_TOP[0] in column 0),
the second memory cells (Fig. 1B: MCs 130B in column 0 in 104) comprise a third memory cell and a fourth memory cell (Fig. 1B: 130Bs) coupled to the second bit line pair within the first column (Fig. 1B: BL_BOT[0], BLB_BOT[0] in column 0), and
the first to fourth memory cells are arranged consecutively within the first column (Fig. 1BL column 0 cells and structure. This limitation is satisfied with N set to 2).
Regarding claim 11, Fujiwara-5671 teaches the memory array of claim 1, further comprising: third memory cells comprise a fifth memory cell and a sixth memory cell coupled to a third bit line pair of the plurality of bit line pairs (Fig. 1B: 130As in 102 in column 1 coupled to BL_TOP[1], BLB_TOP[1]).
Regarding claim 12, Fujiwara-5671 teaches the memory array of claim 11, wherein the first memory cell and the fifth memory cell are coupled to a first word line of the plurality of word lines (Fig. 1B: 130As across column 0 and column 1 are coupled to WL_TOP[N]), and
wherein the second memory cell and the sixth memory cell are coupled to a second word line of the plurality of word lines (Fig. 1B: 130As across column 0 and column 1 are coupled to WL_TOP[1]).
Regarding independent claim 13, Fujiwara-5671 teaches a memory array (Fig. 1B: 100. See para [0020] - para [0021]), comprising:
a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell formed along one of a plurality of columns (Fig. 1B: 113A, 113B MCs formed in column 0),
wherein the first to fourth memory cells are operatively coupled to a first word line, a second word line, a third word line, and a fourth word line, respectively (Fig. 1B: 114s and 118s. See WL_TOP[0], WL_TOP[N], WL_BOT[0], WL_BOT[N]),
wherein the first and second cells (Fig. 1B: 130A MC in 102) are operatively coupled to a first bit line pair (Fig. 1B: BL_TOP[0], BLB_TOP[0]), and
wherein the third and fourth cells (Fig. 1B: 130B MC in 104) are operatively coupled to a second bit line pair (Fig. 1B: BL_BOT[0], BLB_BOT[0]).
Regarding claim 15, Fujiwara-5671 teaches the memory array of claim 13, wherein the first to fourth memory cells are abutted to each along a lateral direction (Fig. 1B: 130As, 130bs), and wherein the first to fourth word lines correspond to four consecutive ones of a plurality of rows, respectively (Fig. 1B: 114s and 118s. See WL_TOP[0], WL_TOP[N], WL_BOT[0], WL_BOT[N]).
Regarding claim 16, Fujiwara-5671 teaches the memory array of claim 13, wherein each of the first to fourth memory cells comprises at least two transistors (Fig. 1B: access transistors of each SRAM 6T cell. See 114 with 116A and 114 with 116B), and
wherein: the two transistors of each of the first and second memory cells (Fig. 1B: access transistors of MCs 130A in 102 in column 0) are coupled to a first bit line and a second bit line of the first bit line pair (Fig. 1B: BL_TOP[0], BLB_TOP[0]), respectively, and
the two transistors of each of the third and fourth memory cells (Fig. 1B: access transistors of MCs 130B in 104 in column 0)are coupled to a third bit line and a fourth bit line of the second bit line pair (Fig. 1B: BL_BOT[0], BLB_BOT[0]), respectively.
Regarding claim 17, Fujiwara-5671 teaches the memory array of claim 16, further comprising: a first source/drain contact extending across the first and second memory cells; a second source/drain contact extending across the first and second memory cells (Fig. 1B: source/drain contacts of 144s are connected to another cell. See 130As column 0 are connected together via source/ drain contacts of access transistors);
a third source/drain contact extending the third and fourth memory cells; and a fourth source/drain contact extending across the third and fourth memory cells (Fig. 1B: source/drain contacts of 144s are connected to another cell. See 130Bs column 0 are connected together via source/ drain contacts of access transistors),
wherein the first and second source/drain contacts are associated with the respective two transistors of the first and second memory cells, and wherein the third and fourth source/drain contacts are associated with the respective two transistors of the third and fourth memory cells (See Fig. 1B: column 0 structure and cells).
Regarding independent claim 18, Fujiwara-5671 teaches a method for making memory arrays, comprising:
forming a plurality of memory cells distributed across a plurality of columns and a plurality of rows; forming a plurality of bit line pairs associated with the plurality of columns; forming a plurality of word lines associated with the plurality of rows; connecting a first set of memory cells of the plurality of memory cells to a first bit line pair of the plurality of bit line pairs; and connecting a second set of memory cells of the plurality of memory cells to a second bit line pair of the plurality of bit line pairs, wherein the first and second sets of memory cells are in one of the plurality of columns.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1).
Regarding claim 20, Fujiwara-5671 teaches the method of claim 18, further comprising: connecting a third set of memory cells of the plurality of memory cells to a third bit line pair of the plurality of bit line pairs (see Fig. 1B: column 1 cells 130A in 102);
connecting a fourth set of memory cells of the plurality of memory cells to a fourth bit line pair of the plurality of bit line pairs, wherein the third and fourth sets of memory cells are in another one of the plurality of columns (see Fig. 1B: column 1 cells 130B in 104);
connecting the first and third sets of memory cells to first two word lines of the plurality of word lines (Fig. 1B: connecting 130A’s in column 0, column 1 using WL_TOP[0] and WL_TOP[N]); and
connecting the second and fourth sets of memory cells to last two word lines of the plurality of word lines (Fig. 1B: connecting 130B’s in column 0, column 1 using WL_BOT[0] and WL_BOT[N]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
5. Claims 9, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara-5671 et al. (US 2019/0385671 A1), in view of Fujiwara-8467 et al. (US 2021/0098467 A1).
Regarding claim 9, Fujiwara-5671 teaches the memory array of claim 1. Fujiwara-5671 teaches 6T SRAM memory cells but is silent with respect to the details of using four contacted polysilicon pitch (4CPP) transistor architecture in the circuit.
Fujiwara-8467 teaches the memory cells are formed based on a four contacted polysilicon pitch (4CPP) transistor architecture (Abstract, para [0017]: " ... four contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture …” Further teaches first to fourth sram memory cells Fig. 9: 450_r0, 410_r1, 450_r2, 410_r3 are operatively coupled to a first word line, a second word line, a third word line, and a fourth word line Fig. 9: WL0, WL 1, WL2, WL3, respectively).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Fujiwara-8467 into the teachings of Fujiwara-5671 such that SRAM cells/ access devices with 4CPP and finfet architecture can be employed in order to increase cell density, shirk array geometry and improve speed.
Regarding claim 14, Fujiwara-5671 and Fujiwara-8467 teach the memory array of claim 13, wherein each of the first to fourth memory cells includes a plurality of transistors formed based on a four contacted polysilicon pitch (4CPP) transistor architecture. (See claim 9 rejection above)
Regarding claim 19, Fujiwara-5671 teaches the method of claim 18.
Fujiwara-5671 teaches the method further comprising:
connecting the plurality of transistors of the first and second sets of memory cells (Fig. 1B: 130A) to consecutive ones of the plurality of word lines (Fig. 1B: WL_TOP, WL_BOT), respectively;
connecting a first one of the first bit line pair (Fig. 1B: BL_TOP[0], BLB_TOP[0]) to at least first two transistors of the first set of memory cell (Fig. 1B: access transistors in 130A);
connecting a second one of the first bit line pair (Fig. 1B: BL_BOT[0], BLB_BOT[0]) to at least second two transistors of the first set of memory cell (Fig. 1B: access transistors in 130B);
connecting a first one of the second bit line pair (Fig. 1B: BL_BOT[0]) to at least first two transistors of the second set of memory cell (Fig. 1B: left access transistors in 130B); and
connecting a second one of the second bit line pair (Fig. 1B: BLB_BOT[0]) to at least second two transistors of the second set of memory cell (Fig. 1B: right access transistor in 130B).
Fujiwara-5671 teaches 6T SRAM memory cells but is silent with respect to each of the first and second sets of memory cells comprises a plurality of transistors formed based on a four contacted polysilicon pitch (4CPP) architecture.
Fujiwara-8467 teaches the memory cells are formed based on a four contacted polysilicon pitch (4CPP) transistor architecture (Abstract, para [0017]: " ... four contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture …” Further teaches first to fourth sram memory cells Fig. 9: 450_r0, 410_r1, 450_r2, 410_r3 are operatively coupled to a first word line, a second word line, a third word line, and a fourth word line Fig. 9: WL0, WL 1, WL2, WL3, respectively).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Fujiwara-8467 into the teachings of Fujiwara-5671 such that SRAM cells/ access devices with 4CPP and finfet architecture can be employed in order to increase cell density, shirk array geometry and improve speed.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
KOLAR (US 2022/0383939 A1): Fig. 1-Fig. 6 disclosure applicable for all claims.
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See esp. Fig. 2 bit line structure and column mux’ing process.
YANG (US 2021/0201972 A1): Fig. 1-Fig. 7 disclosure applicable for all claims.
Huang (US 2021/0082495 A1): Fig. 1-Fig. 7 disclosure applicable for all claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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