Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 10 are presented for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/03/2025 was received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3 and 6 – 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fuller, U.S. Publication 2020/0371872 (herein Fuller).
Regarding claim 1, Fuller discloses: A built-in self-test device, adapted to fuse intellectual properties (paragraph 0014), and comprising: at least one fuse element, each of the at least one fuse element corresponding to the fuse IPs and providing corresponding at least one fuse bit value, and each of the at least one fuse element further comprising a check bit for providing a check bit value (figure 1, element 130; paragraph 0015, 0018); a computing circuit, coupled to the at least one fuse element (figure 1, element 110; paragraph 0015 “As an example, logic block 110, or another logic block, processor, or another controller, may provide information referred to as an integrity vector”; a power supply circuit, controlled by a processor to provide power to the at least one fuse element (paragraph 0015 “Electric-fuse based technology may include subjecting metal or polysilicon to high-voltages, causing electromigration”); and the processor, coupled to the computing circuit, wherein the processor controls the computing circuit to obtain the fuse bit values and the check bit value from the at least one fuse element, and performs a logical operation based on the fuse bit values and the check bit value to generate a check result (figure 5, element 510), wherein the check result is used to indicate whether a blown error occurs in the at least one fuse element (figure 5, element 510 ,520).
Regarding claim 2, Fuller discloses: the logical operation is a parity check or a cyclic redundancy check, wherein a value of the check bit value in the check bit is set based on a preset fuse bit value corresponding to the at least one fuse element (paragraph 0019).
Regarding claim 3, Fuller discloses: an XOR gate circuit, coupled to the at least one fuse element, and configured to perform an XOR operation based on the fuse bit values and the check bit value in each of the at least one fuse element to respectively produce a first logical result (figure 4B); and an OR gate circuit, coupled to the XOR gate circuit, and configured to generate the check result based on the first logical result (figure 4B).
Regarding claim 6, Fuller discloses: An error detection method, adapted to fuse intellectual properties (paragraph 0014), and comprising: obtaining at least one fuse bit value and a check bit value from at least one fuse element, wherein each of the at least one fuse element corresponds to the fuse IPs and provides the corresponding at least one fuse bit value, and each of the at least one fuse element further comprises a check bit to provide the check bit value (figure 5, element 510); performing a logical operation based on the fuse bit values and the check bit value to generate a check result (figure 4B; figure 5, element 510, 520); and determining whether the at least one fuse element has a blown error based on the check result (figure 5, element 510, 520).
Regarding claim 7, Fuller discloses: a value of the check bit value in the check bit is set based on a preset fuse bit value corresponding to the at least one fuse element (paragraph 0019).
Regarding claim 8, Fuller discloses: wherein the logical operation is a parity check, wherein the step of performing the logical operation based on the fuse bit values and the check bit value to generate the check result comprises: performing an XOR operation based on the fuse bit values and the check bit value in each of the at least one fuse element to respectively produce a first logical result (figure 4B); and generating the check result based on the first logical result (figure 4B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Fuller, in view of Aal et al., U.S. Publication 2022/0043056 (herein Aal).
Regarding claims 4 and 10, Fuller does not explicitly teach: wherein the processor further controls the computing circuit and the power supply circuit to perform one of a voltage shock test, a step-down shmoo test, and a step-up shmoo test on the at least one fuse element.
Aal teaches: wherein the processor further controls the computing circuit and the power supply circuit to perform one of a voltage shock test, a step-down shmoo test, and a step-up shmoo test on the at least one fuse element (paragraph 0068, 85, 0086, 0094, 0097).
One of ordinary skill in the art, at the time of the effective filing date of the invention, would find it obvious to combine the teaching of Fuller: A built-in self-test device, adapted to fuse intellectual properties; with the teaching of Aal: shmoo testing with fuses for the purpose of characterizing elements (paragraph 0068, 85, 0086, 0094, 0097). Testing fuses is well-known in the art (abstract). Shmoo testing with fuses well-known design choice in the art (paragraph 0068, 85, 0086, 0094, 0097). One of ordinary skill in the art would recognize the use of well-known design choice would yield a predictable result.
Allowable Subject Matter
Claims 5 and 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Closest Prior Arts of Record
Maeno, U.S. Publication 2002/0062458 (herein Maeno)
Maeno teaches: A semiconductor integrated circuit device has a redundancy circuit such that when a parallel/serial conversion circuit converts the separation information of a program element group such as one fuse element group to serial data, the serial data is transmitted through a serial/parallel conversion circuit, thus controlling circuits to be controlled such as a plurality of RAMs. Further by introducing a CRC technique in the parallel/serial conversion circuit, even when there is an error input such as cutting error of the fuse element, the information may be reproduced.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ito, Yutaka et al. US 20050281112 A1
Maeno, Hideshi US 20020062458 A1
Hein; Thomas et al. US 20260030096 A1
Otsuka; Nobuaki US 20060227617 A1
Fujiwara; Yoshinori et al. US 20240071560 A1
Kasorla; Yoav et al. US 9136012 B1
Roy; Tanmoy et al. US 8458545 B2
each of the at least one fuse element corresponding to the fuse IPs and providing corresponding at least one fuse bit value, and each of the at least one fuse element further comprising a check bit for providing a check bit value;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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