Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 11-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fan et al., US 2024/0242649 A1 (hereinafter “Fan”).
Regarding claim 1, Fan discloses a stage circuit (FIGS. 4-5 and 8-9 generally [0076]-[0084] and [0106]-[0121] and [0158] and [0184]) comprising:
an output unit (FIG. 5 at [0106]-[0121] M01, M02 and C1, first output 13 and second output 22 in combination with energy storage 41) which supplies a scan signal to an output terminal (FIGS. 4-5 and [0106]-[0121] and output terminal G1) in response to a voltage of a first node (FIG. 5, GT2) and a second node (FIG. 5, GT1);
an input unit (FIG. 5, first node control I1) which outputs a carry signal or a start signal input (FIGS. 3-55 and [0065] and [0105]-[0110]) to a first input terminal (FIG. 5, N1) in response to a clock signal (FIG. 5, and [0106]-[0121] and K1, K2, K3 clock signals);
a first transistor (FIG. 5, M7) connected between the input unit (FIG. 5, first node control I1) and the second node (FIG. 5, GT1) and set to a turn-on state during a driving period (FIGS. 5-6 and [0127]-[0133]); and
a controller (FIG. 5 and first node control circuit 11 and [0106]-[0121]) connected between the input unit (FIG. 5, first node control I1) and the first transistor (FIG. 5, M7) or between the first transistor and the second node (see above, condition satisfied; alternative interpretation, FIG. 5 controller 21, second node is GT1), wherein the controller controls an electrical connection between the input unit (FIG. 5, first node control I1) and the second node (FIG. 5, GT1, electrical connection made through at least M1 ) .
Regarding claim 2, Fan discloses the stage circuit according to claim 1 (see above), wherein the controller is connected between the input unit and the first transistor (FIG. 5, 11 between I1 and M7).
Regarding claim 3, Fan discloses the stage circuit according to claim 1 (see above), wherein the controller (in a second interpretation controller is considered FIG. 5 and first second node control circuit 21) is connected between the first transistor (M7) and the second node (in a second interpretation controller is considered FIG. 5 and first second node control circuit 21 and the second node is GT2).
Regarding claim 4, Fan discloses the stage circuit according to claim 1 (see above), wherein the controller includes a second transistor (FIG. 5 and first node control circuit 11 and M3 at [0106]-[0121]).
Regarding claim 5, Fan discloses the stage circuit according to claim 4 (see above), wherein a gate electrode of the second transistor is connected to the first node (FIG. 5 and first node control circuit 11 and M3 at [0106]-[0121] which is connected to GT2).
Regarding claim 6, Fan discloses the stage circuit according to claim 4 (see above), wherein a gate electrode of the second transistor (FIG. 5 and first node control circuit 11 and M3 at [0106]-[0121]) is connected to a control input terminal (FIG. 5 node of GT2 connected to C2 and V01), and the control input terminal receives a control signal (FIG. 5 node of GT2 connected to C2 and V01 control signal).
Regarding claim 11, Fan discloses the stage circuit according to claim 4 (see above), wherein the first transistor and the second transistor are transistors of different types ([0002] and [0042] and [0122]-[0124] first node transistors of only one type while other transistors of another type).
Regarding claim 12, Fan discloses the stage circuit according to claim 11 (see above), wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor ([0002] and [0042] and [0122]-[0124] first node transistors of only one type while other transistors of another type).
Regarding claim 13, Fan discloses the stage circuit according to claim 11 (see above), wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor ([0002] and [0042] and [0122]-[0124] first node transistors of only one type while other transistors of another type).
Regarding claim 14, Fan discloses the stage circuit according to claim 4 (see above), wherein the first transistor and the second transistor are P-type transistors ([0149] all of P-type).
Regarding claim 15, Fan discloses the stage circuit according to claim 4 (see above), wherein the first transistor and the second transistor are N-type transistors ([0002] known to use only one type over the other).
Regarding claim 16, Fan discloses the stage circuit according to claim 1 (see above), further comprising: a driver (FIG. 5, M3 serves as driver) which controls the voltage of the first node (FIG. 5, GT2), wherein the controller (in an embodiment 21 can serve as the controller) is connected between the driver (M3) and the first transistor (FIG. 5, M7).
Regarding claim 17, Fan discloses the stage circuit according to claim 1 (see above), further comprising: a driver (FIG. 5, M3 serves as driver)which controls the voltage of the first node (GT2), wherein the controller (FIG. 5, M1) is connected between the input unit (FIG. 5, I1) and the driver (M3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Yamakazi et al., US 2012/0001955 A1 (hereinafter “Yamakazi”).
Regarding claim 7, Fan discloses the stage circuit according to claim 6 (see above).
However, Fan does not explicitly disclose wherein one frame period includes a display scan period, in which a data signal is received, and a self-scan period, in which light is emitted while maintaining the data signal, and the control signal is set to a voltage level at which the second transistor is turned on during the display scan period, and is set to a voltage level at which the second transistor is turned off during the self-scan period.
In the same field of endeavor, Yamakazi discloses wherein one frame period includes a display scan period (FIG. 10 with writing period), in which a data signal is received (FIG. 10 with writing period at [0155]-[0160]), and a self-scan period (FIG. 10 holding period), in which light is emitted while maintaining the data signal (FIG. 10 holding period and [0155]), and the control signal is set to a voltage level at which the second transistor is turned on during the display scan period (FIGS. 8A-11 and [0155]-[0169]), and is set to a voltage level at which the second transistor is turned off during the self-scan period (FIGS. 8A-11 and [00124]-[00130] and [0150] and [0155]-[0169]).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the stage driver of Fan to incorporate display driving as disclosed by Yamakazi because the references are within the same field of endeavor, namely, stage circuits for a display device. The motivation to combine these references would have been to improve reduction of light loss and thereby reducing power consumption (see Yamakazi at least at [0002]-[0009]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Lin et al., US 2011/0150169 A1 (hereinafter “Lin”).
Regarding claim 8, Fan discloses the stage circuit according to claim 4 (see above).
However, Fan does not explicitly disclose wherein the second transistor further includes a second gate electrode, and the second gate electrode is electrically connected to a gate electrode of the second transistor.
In the same field of endeavor, Lin discloses a shift register stage circuit (abstract) wherein the second transistor further includes a second gate electrode (FIGS. 1 and 4 and T2 at [0014] and [0035]), and the second gate electrode is electrically connected to a gate electrode of the second transistor (FIGS. 1 and 4 and T2 at [0014] and [0035]).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the stage driver of Fan to incorporate the dual gate electrode as disclosed by Lin because the references are within the same field of endeavor, namely, stage circuits for a display device. The motivation to combine these references would have been to improve conduction current using a dual gate transistor (see Lin at least at [0007]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Regarding claim 9, Fan discloses the stage circuit according to claim 4 (see above).
However, Fan does not explicitly disclose wherein the second transistor further includes a second gate electrode, and the second gate electrode receives a direct current voltage.
In the same field of endeavor, Lin discloses a shift register stage circuit (abstract) wherein the second transistor further includes a second gate electrode (FIGS. 1 and 4 and T2 at [0014] and [0035]), and the second gate electrode receives a direct current voltage (FIGS. 1 and 4 and T2 at [0014] and [0035]).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the stage driver of Fan to incorporate the dual gate electrode as disclosed by Lin because the references are within the same field of endeavor, namely, stage circuits for a display device. The motivation to combine these references would have been to improve conduction current using a dual gate transistor (see Lin at least at [0007]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Shin et al., US 2024/0221624 A1 (hereinafter “Shin”).
Regarding claim 10, Fan discloses the stage circuit according to claim 4 (see above).
However, Fan does not explicitly disclose wherein the second transistor further includes a second gate electrode, and the second gate electrode receives an alternating current voltage.
In the same field of endeavor, Shin discloses a shift register circuit (FIGS. 7-9 generally) wherein the second transistor further includes a second gate electrode (FIG. 9 and T7c having a second gate and [0083]-[0084]), and the second gate electrode receives an alternating current voltage (see FIGS. 9 and 12 and [0091]-[0092]).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the stage driver of Fan to incorporate the dual gate electrode as disclosed by Shin because the references are within the same field of endeavor, namely, stage circuits for a display device. The motivation to combine these references would have been to minimize or reduce leakage current (see Shin at least at [0007] and [0143]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2019/0172397 A1 (hereinafter “Lee”) in view of Fan et al., US 2024/0242649 A1 (hereinafter “Fan”).
Regarding claim 18, Lee discloses display device (FIGS. 1-2 and 100 at [0033]-[0035]) comprising: pixels connected to scan lines (FIGS. 2-3 , with PXL connected to Scan and EM lines as disclosed at [0035]), emission control lines (FIGS. 2-3, with PXL connected to Scan and EM lines as disclosed at [0035]), and data lines (FIG. 2-3, with PXL connected to Vdata lines as disclosed at [0039]); a scan driver which supplies a scan signal to the scan lines (FIG. 5 and scan driver 131 and [0045]-[0046]); and an emission driver which supplies an emission control signal to the emission control lines (FIG. 5 and emission driver 132 and [0045]-[0046]), wherein a stage circuit is included in at least one selected from the scan driver and the emission driver (FIG. 6, and [0050]-[0052] and stages ST1-4 of emission driver 132).
However, Lee does not explicitly discloses wherein the stage circuit comprises: an output unit which supplies the scan signal or the emission control signal to an output terminal in response to a voltage of a first node and a second node; an input unit which outputs a carry signal or a start signal input to a first input terminal in response to a clock signal; a first transistor connected between the input unit and the second node and set to a turn-on state during a driving period; and a controller connected between the input unit and the first transistor or between the first transistor and the second node, wherein the controller controls an electrical connection between the input unit and the second node.
In the same field of endeavor, Fan discloses wherein the stage circuit comprises: an output unit (FIG. 5 at [0106]-[0121] M01, M02 and C1, first output 13 and second output 22 in combination with energy storage 41) which supplies a scan signal to an output terminal (FIGS. 4-5 and [0106]-[0121] and output terminal G1) in response to a voltage of a first node (FIG. 5, GT2) and a second node (FIG. 5, GT1);
an input unit (FIG. 5, first node control I1) which outputs a carry signal or a start signal input (FIGS. 3-55 and [0065] and [0105]-[0110]) to a first input terminal (FIG. 5, N1) in response to a clock signal (FIG. 5, and [0106]-[0121] and K1, K2, K3 clock signals);
a first transistor (FIG. 5, M7) connected between the input unit (FIG. 5, first node control I1) and the second node (FIG. 5, GT1) and set to a turn-on state during a driving period (FIGS. 5-6 and [0127]-[0133]); and
a controller (FIG. 5 and first node control circuit 11 and [0106]-[0121]) connected between the input unit (FIG. 5, first node control I1) and the first transistor (FIG. 5, M7) or between the first transistor and the second node (see above, condition satisfied; alternative interpretation, FIG. 5 controller 21, second node is GT1), wherein the controller controls an electrical connection between the input unit (FIG. 5, first node control I1) and the second node (FIG. 5, GT1, electrical connection made through at least M1 ) .
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display device of Lee to incorporate the stage driving circuit as disclosed by Fan because the references are within the same field of endeavor, namely, display driving devices and components thereof. The motivation to combine these references would have been to improve the driving capability while reducing leakage current (see Fan at least at [0090] and [0105]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Regarding claim 19, Lee in view of Fan discloses the display device according to claim 18 (see above), wherein the controller includes a second transistor (Fan FIG. 5 and first node control circuit 11 and M3 at [0106]-[0121]) and; wherein a gate electrode of the second transistor is connected to the first node (Fan FIG. 5 and first node control circuit 11 and M3 at [0106]-[0121] which is connected to GT2).
Regarding claim 20, Lee discloses an electronic device (FIG. 1 generally), comprising: a processor to provide input image data (controller 110 at FIG. 1 and [0042]); and a display device to display an image based on the input image data (FIG. 1, and [0047]-[0048] data used to display an image); wherein the display device comprising: pixels connected to scan lines (FIGS. 2-3 , with PXL connected to Scan and EM lines as disclosed at [0035]), emission control lines (FIGS. 2-3, with PXL connected to Scan and EM lines as disclosed at [0035]), and data lines (FIG. 2-3, with PXL connected to Vdata lines as disclosed at [0039]); a scan driver which supplies a scan signal to the scan lines (FIG. 5 and scan driver 131 and [0045]-[0046]); and an emission driver which supplies an emission control signal to the emission control lines (FIG. 5 and emission driver 132 and [0045]-[0046]), wherein a stage circuit is included in at least one selected from the scan driver and the emission driver (FIG. 6, and [0050]-[0052] and stages ST1-4 of emission driver 132).
However, Lee does not explicitly discloses wherein the stage circuit comprises: an output unit which supplies the scan signal or the emission control signal to an output terminal in response to a voltage of a first node and a second node; an input unit which outputs a carry signal or a start signal input to a first input terminal in response to a clock signal; a first transistor connected between the input unit and the second node and set to a turn-on state during a driving period; and a controller connected between the input unit and the first transistor or between the first transistor and the second node, wherein the controller controls an electrical connection between the input unit and the second node.
In the same field of endeavor, Fan discloses wherein the stage circuit comprises: an output unit (FIG. 5 at [0106]-[0121] M01, M02 and C1, first output 13 and second output 22 in combination with energy storage 41) which supplies a scan signal to an output terminal (FIGS. 4-5 and [0106]-[0121] and output terminal G1) in response to a voltage of a first node (FIG. 5, GT2) and a second node (FIG. 5, GT1);
an input unit (FIG. 5, first node control I1) which outputs a carry signal or a start signal input (FIGS. 3-55 and [0065] and [0105]-[0110]) to a first input terminal (FIG. 5, N1) in response to a clock signal (FIG. 5, and [0106]-[0121] and K1, K2, K3 clock signals);
a first transistor (FIG. 5, M7) connected between the input unit (FIG. 5, first node control I1) and the second node (FIG. 5, GT1) and set to a turn-on state during a driving period (FIGS. 5-6 and [0127]-[0133]); and
a controller (FIG. 5 and first node control circuit 11 and [0106]-[0121]) connected between the input unit (FIG. 5, first node control I1) and the first transistor (FIG. 5, M7) or between the first transistor and the second node (see above, condition satisfied; alternative interpretation, FIG. 5 controller 21, second node is GT1), wherein the controller controls an electrical connection between the input unit (FIG. 5, first node control I1) and the second node (FIG. 5, GT1, electrical connection made through at least M1 ) .
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display device of Lee to incorporate the stage driving circuit as disclosed by Fan because the references are within the same field of endeavor, namely, display driving devices and components thereof. The motivation to combine these references would have been to improve the driving capability while reducing leakage current (see Fan at least at [0090] and [0105]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xu et al., US 2020/0294461 A1;
Jang, US 2019/0164498 A1;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARVESH J NADKARNI whose telephone number is (571)270-7562. The examiner can normally be reached 8AM-5PM M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached at (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SARVESH J NADKARNI/Examiner, Art Unit 2621