DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 9 and 17.
b. Pending: 1-20.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,243,592. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 differs from claim 9 of parent 12, 243,592 by reciting:
A plurality of OTP memory cells arranged in a plurality of columns; a respective bit line connectable to the OTP cells of each column; a multiplexer selecting one of the bit lines for a read operation; applying the patented sensing and feedback arrangement to the selected bit line. These limitations represent an obvious duplication and conventional organization of the OTP memory cell and bit-line sensing circuit of patented claim 9. Providing multiple claimed OTP cells in columns with respective bit lines would have been an obvious implementation for increasing memory capacity. Providing a multiplexer to select one of those bit lines would likewise have been an obvious and predictable way to permit the patented sense amplifier and feedback circuit to access a selected column while reducing duplication of sensing circuitry.
The resulting device performs the same function recited in patented claim 9: the sense amplifier reads an OTP cell through its bit line, and the feedback circuit extending between the sense-amplifier output and that bit line suppresses the bit-line current after a first value is sensed.
Accordingly, claim 1 constitutes no more than an obvious array-level implementation of the invention already claimed in claim 9 of US Patent 12,243,592 and is therefore unpatentable for nonstatutory obviousness-type double patenting.
Claim 2 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 2 of US Patent No 12,243,592.
Claim 3 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 3 of US Patent No 12,243,592.
Claim 4 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 4 of US Patent No 12,243,592.
Claim 5 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 5 of US Patent No 12,243,592.
Claim 6 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of US Patent No 12,243,592.
Claim 7 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 7 of US Patent No 12,243,592.
Claim 8 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 6 of US Patent No 12,243,592.
Claim 9 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 9 of US Patent No 12,243,592.
Claim 10 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 9 of US Patent No 12,243,592.
Claim 11 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 10 of US Patent No 12,243,592.
Claim 12 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 11 of US Patent No 12,243,592.
Claim 13 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 12 of US Patent No 12,243,592.
Claim 14 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 13 of US Patent No 12,243,592.
Claim 15 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 14 of US Patent No 12,243,592.
Claim 16 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 15 of US Patent No 12,243,592.
Claim 17 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 17 of US Patent No 12,243,592.
Claim 18 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 18 of US Patent No 12,243,592.
Claim 19 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 19 of US Patent No 12,243,592.
Claim 20 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 6, 15 of US Patent No 12,243,592.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 7, 10, 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 6 recites the limitation “first transistor” in line 2. There is insufficient antecedent basis for this limitation in the claim, as this is the first recitation. For the purpose of examination, it is assumed that "first transistor" is instead "a first transistor".
Claim 7 recites the limitation “the second transistor” in line 1. There is insufficient antecedent basis for this limitation in the claim, as this is the first recitation. For the purpose of examination, it is assumed that "the second transistor " is instead "a second transistor ".
Claim 10 recites the limitation “first transistor” in line 2. There is insufficient antecedent basis for this limitation in the claim, as this is the first recitation. For the purpose of examination, it is assumed that "first transistor" is instead "a first transistor".
Claim 12 recites the limitation “the feedback current” in line 2. There is insufficient antecedent basis for this limitation in the claim, as this is the first recitation. For the purpose of examination, it is assumed that "the feedback current" is instead "a feedback current".
Claim 13 recites the limitation “the predetermined voltage node” in line 1. There is insufficient antecedent basis for this limitation in the claim, as this is the first recitation. For the purpose of examination, it is assumed that " the predetermined voltage node" is instead "a predetermined voltage node".
Claim 14 recites the limitation “the current discharge path” in line 1. There is insufficient antecedent basis for this limitation in the claim, as this is the first recitation. For the purpose of examination, it is assumed that "the current discharge path" is instead "a current discharge path".
Claim 15 is rejected under 35 U.S.C. 112(b) due to its dependency on claim 14.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11, 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ha PG PUB 20200219570 (hereinafter Ha), in view of Cernea PG PUB 20070109889 (hereinafter Cernea).
Regarding independent claim 1, Ha teaches a memory device (title of Ha, figure 1 of Ha) comprising:
a plurality of one-time programmable memory cells (figure 1 of Ha, figure 5 of Ha, [0036] of Ha, “… cell array circuit 100 includes at least an OTP cell array 110 …”), wherein the plurality of one- time programable memory cells are arranged on a plurality of columns (BL direction in figure 1 of Ha, figure 5 of Ha), each of the plurality of columns comprising a first plurality of one-time programable memory cells (cells linked to one of BL1-BLn in figure 1 of Ha, each cell includes antifuse AF and rad transistor TR as shown in figure 2) and a bit line (one of BL1-BLn in figure 1 of Ha) connectable to each of the first plurality of one-time programable memory cells;
a multiplexer to select one of a plurality of bit lines for a read operation (column decoder 210 in figure 1 of Ha is connected between bit lines BL and write/sensing circuit 220 and selects addressed bit lines based on column address CADDR. It therefore performs the recited multiplexer function by selectively coupling an addressed bit line to write/sensing circuit 220, [0041] of Ha, “…column decoder 210 is coupled to the OTP cell array 110 through the bit-lines BL. The column decoder 210 selects some of the bit-lines BL based on the column address CADDR…”);
a sense amplifier (220 in figure 1 of Ha, [0043] of Ha, “…sense amplifier may perform a read operation for sensing the data stored in the OTP memory cells and providing the read data to the outside as output data DO…”) connected to the selected bit line, wherein the sense amplifier is operative to sense data from the selected bit line.
But Ha does not teach a feedback circuit connected between an output of the sense amplifier and the selected bit line, wherein the feedback circuit is operative to suppress a bit line current of the selected bit line in response to the sense amplifier sensing a first value from the bit line.
However, Cernea teaches in figure 14 and [0127]-[0134] sense module 480 connected to bit line 36 through isolation transistor 482 and including sense amplifier 600 and bit-line pull down circuit 486. Sense amplifier 600 produces sensed output SEN2 and its inverse singal INV. INV controls n-transistor 487 of pull down circuit 486, which is coupled back to bit line 36 through sense node 481, voltage clamp 610, and isolation transistor 482. Thus, the INV/control path and pull down circuit 486 constitute a feedback circuit extending from the sense amplifier output back to the bit line. The sense amplifier determines whether the sensed bit line conduction is above or below a predetermined value. When the higher current value is sensed, SEN2 becomes LOW and INV becomes HIGH, activating pull down circuit 486. The circuit pulls bit line 36 to ground and thereby turns off, i.e., suppresses, the bit line conduction current ([0133]-[0134], [0146]-[0148] of Cernea, “…sense amplifier 600 senses the conduction current through the sense node 481 and determines whether the conduction current is above or below a predetermined value…”)
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Ha’s sense amplifier read path by providing Cernea’s output controlled bit line pull down feedback circuit on the selected bit line side of Ha’s column decoder. Cernea teaches using this circuit to identify a sensed high current state and then turn off the corresponding bit line current, thereby reducing source line bias error and improving the accuracy of subsequent sensing. Applying Cernea known current suppression technique to Ha OTP read circuit would have provided the same benefit.
Regarding claim 2, the combination of Ha and Cernea teaches the memory device of claim 1, wherein the feedback circuit comprises a decision logic circuit (Cernea teaches discriminator circuit 650 and latch 660, which determine the sensed current state and generate control signals INV and LAT, see figure 14, [0129], [0133]-[0134] of Cernea) and a first switch (isolation gate /transistor 630 in figure 14), wherein the decision logic circuit is operative to selectively switch off the first switch to shut down a current discharge path for the bit line (Cernea teaches in figure 14, 15 and [0146]-[0147], when a high current condition is detected, the discriminator and latch cause INV to become HIG and LAT to become LOW, thereby disabling isolation gate 630, and blocking sense node 481 from internal node 631).
Regarding claim 3, the combination of Ha and Cernea teaches the memory device of claim 2, wherein the first switch (isolation gate/transistor 630 in figure 14 of Cernea) is connected between the bit line (bit line in figure 14 of Cernea) and the sense amplifier (SEN in figure 14 of Cernea), and wherein the decision logic circuit (discriminator circuit 650 and latch 660 in figure 14 of Cernea) is connected between the output of the sense amplifier (SEN in figure 14 of Cernea) and the first switch (isolation gate/transistor 630 in figure 14 of Cernea).
Regarding claim 4, the combination of Ha and Cernea teaches the memory device of claim 2, the feedback circuit further comprises a second switch (487 in figure 14 of Cernea) connected between a predetermined voltage node (ground in figure 14 of Cernea) and the bit line.
Regarding claim 5, the combination of Ha and Cernea teaches the memory device of claim 4, wherein the second switch (487 in figure 14 of Cernea) is connected to the decision logic circuit (discriminator circuit 650 and latch 660 in figure 14 of Cernea), and wherein the decision logic circuit (discriminator circuit 650 and latch 660 in figure 14 of Cernea) switches on the second switch to connect the bit line to the predetermined voltage node.
Regarding claim 6, the combination of Ha and Cernea teaches the memory device of claim 1, wherein each of the plurality of one-time programmable memory cells comprises a second transistor (AF in figure 2 of Ha) connected in series with first transistor (TR in figure 2 of Ha), wherein the second transistor (AF in figure 2 of Ha) is programmable between a first state and a second state.
Regarding claim 7, the combination of Ha and Cernea teaches the memory device of claim 1, wherein the second transistor (AF in figure 2 of Ha) is programmed by applying a pre-determined current across the second transistor ([0051] of Ha, [0051] of Ha, “…the anti-fuse AF may include a dielectric material between two conductors. The dielectric material may be broken and programmed by applying a high voltage between the two conductors for a sufficient time...”)
Regarding claim 8, the combination of Ha and Cernea teaches the memory device of claim 1, wherein the feedback circuit comprises a third transistor (487 in figure 14 of Cernea).
Regarding independent claim 9, the combination of Ha and Cernea teaches substantially the same memory device recited in claim 1. The term “disrupt a bit line current” is at least as broad as “suppress a bit line current”. Cernea teaches pulling bit line 36 to ground through feedback controlled pull down circuit 486, thereby turning off the bit line conduction current. Accordingly, claim 9 is rejected for the same reasons presented above regarding claim 1.
Claim 10 is rejected for the same reasons presented above regarding claim 6.
Regarding claim 11, the combination of Ha and Cernea teaches the memory device of claim 9, wherein the feedback circuit comprises a third transistor (487 in figure 14 of Cernea), wherein a source/drain of the third transistor is connected to the selected bit line (bit line 36 in figure 14 of Cernea), a drain/source of the third transistor is connected to a predetermined voltage node (ground in figure 14 of Cernea), and a gate of the third transistor is connected to the output of the sense amplifier (gate of 487 is controlled by INV, which is generated from sensed results SEN2).
Claim 16 is rejected for the same reasons presented above regarding claim 8.
Claim 17 recites the method counterpart of memory device of claim 1, thus is rejected for the same reasons presented above regarding claim 1.
Claim 18 is rejected for the same reasons presented above regarding claim 2.
Claim 19 is rejected for the same reasons presented above regarding claim 6.
Claim 20 is rejected for the same reasons presented above regarding claim 11.
Allowable Subject Matter
Claim 12-15 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and under nonstatutory double patenting set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is Cernea (US 20070109889 Al).
Cernea discloses Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In this way, sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells.
Regarding claim 12 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the decision logic circuit is operative to selectively switch on the first switch to inject the feedback current into the selected bit line.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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