Prosecution Insights
Last updated: July 17, 2026
Application No. 19/069,194

DISPLAY DEVICE

Final Rejection §103
Filed
Mar 03, 2025
Priority
Jun 19, 2023 — RE 10-2023-0078117 +1 more
Examiner
NADKARNI, SARVESH J
Art Unit
2629
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
1y 6m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
370 granted / 512 resolved
+10.3% vs TC avg
Moderate +14% lift
Without
With
+14.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
16 currently pending
Career history
537
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
96.1%
+56.1% vs TC avg
§102
2.0%
-38.0% vs TC avg
§112
0.9%
-39.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 512 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Regarding the double patenting rejection, Examiner respectfully submits it is sustained as properly addressed below. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,243,483 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the currently examined application are anticipated by or are obvious variants of the issued patent claims as clearly illustrated below. Currently Examined Application 19/069,194 US Patent No. 12,243,483 B2. 1. A display device comprising: a substrate comprising a display area in which emission areas are arranged, and a non-display area located around the display area; and a circuit layer on the substrate, wherein the circuit layer comprises: light emitting pixel drivers arranged in the display area along a first direction and a second direction; first auxiliary lines extending in the first direction; second auxiliary lines extending in the second direction; connection auxiliary electrodes adjacent to crossings between the first auxiliary lines and the second auxiliary lines and spaced apart from the first auxiliary lines; and auxiliary protrusion electrodes protruding from the second auxiliary lines, and electrically connected to the connection auxiliary electrodes through an auxiliary connection hole of auxiliary connection holes; wherein one of the first auxiliary lines bends around a corresponding one of the connection auxiliary electrodes. 1. A display device comprising: a substrate comprising a display area in which emission areas are arranged, and a non-display area located around the display area; a circuit layer on the substrate; and an element layer on the circuit layer, and comprising light emitting elements positioned in the emission areas, wherein the circuit layer comprises: light emitting pixel drivers electrically connected to the light emitting elements; data lines electrically connected to the light emitting pixel drivers; first auxiliary lines extending in a first direction crossing the data lines and positioned in the light emitting pixel drivers; and second auxiliary lines extending in a second direction crossing the first direction and in parallel with the data lines, the second auxiliary lines being paired with respective ones of the data lines, wherein the first auxiliary lines comprise a first bypass auxiliary line electrically connected to a first data line of the data lines that is adjacent to the non-display area in the first direction, wherein the second auxiliary lines comprise a second bypass auxiliary line paired with a second data line spaced farther from the non-display area than the first data line in the first direction among the data lines, wherein the circuit layer further comprises: a first connection auxiliary electrode adjacent to a crossing between the first bypass auxiliary line and the second bypass auxiliary line, and spaced apart from the first bypass auxiliary line; a first connection line connecting the first bypass auxiliary line to the first connection auxiliary electrode; and a first auxiliary protrusion electrode protruding from the second bypass auxiliary line, and electrically connected to the first connection auxiliary electrode through an auxiliary connection hole of auxiliary connection holes. (commonly known in the art for producing pixel density) Claim 2. Claim 2. Claim 3. Claim 3. Claim 4. Claim 3. Claim 5. Claim 5. Claim 6. Claim 6. Claim 7. Claim 7. Claim 8. Claim 10. Claim 9. Claim 10. Claim 10. Claim 8. Claim 11. An electronic device comprising: a display device displaying an image; (commonly known in the art) a processor executing the application and transmitting an image data signal and an input control signal to the display device; (commonly known in the art) and a memory storing an application; (commonly known in the art) a power supply module supplying power to the display device, (commonly known in the art) wherein the display device comprises: a substrate comprising a display area in which emission areas are arranged, and a non-display area around the display area; and a circuit layer on the substrate, wherein the circuit layer comprises: light emitting pixel drivers arranged in the display area in a first direction and a second direction; data lines transmitting a data signal to the light emitting pixel drivers; first auxiliary lines extending in the first direction; second auxiliary lines extending in the second direction and being adjacent to respective ones of the data lines; connection auxiliary electrodes adjacent to crossings between the first auxiliary lines and the second auxiliary lines and spaced apart from the first auxiliary lines; and auxiliary protrusion electrodes protruding from the second auxiliary lines, and overlapped with respective ones of the connection auxiliary electrodes in a third direction; wherein one of the first auxiliary lines bends around a corresponding one of the connection auxiliary electrodes. Claim 12. A display device comprising: a substrate comprising a display area in which emission areas are arranged, and a non-display area around the display area; a circuit layer on the substrate; and an element layer on the circuit layer, and comprising light emitting elements positioned in the emission areas, wherein the circuit layer comprises: light emitting pixel drivers electrically connected to the light emitting elements; data lines electrically connected to the light emitting pixel drivers; first auxiliary lines extending in a first direction crossing the data lines and positioned in the light emitting pixel drivers; second auxiliary lines extending in a second direction crossing the first direction and in parallel with the data lines, the second auxiliary lines being paired with respective ones of the data lines; connection auxiliary electrodes adjacent to crossings between the first auxiliary lines and the second auxiliary lines and spaced apart from the first auxiliary lines; and auxiliary protrusion electrodes protruding from the second auxiliary lines, and electrically connected to the connection auxiliary electrodes through an auxiliary connection hole of auxiliary connection holes. (commonly known in the art for producing pixel density) Claim 12. Claim 13. Claim 13. Claim 13. Claim 14. Claim 14. Claim 15. Claim 15 Claim 16. Claim 16. Claim 17. Claim 17. Claim 18. (also similar to issued claim 11) Claim 18. Claim 19. Claim 19. Claim 20. Claim 20. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Li, US 2024/0006574 A1 (hereinafter “Li”) in view of Li, US 2024/0155902 A1 (hereinafter “Li ‘902”). Regarding claim 1, Li discloses a display device (Li at Abstract and FIG. 27, [0431]-[0432] and display device 100) comprising: a substrate (FIGS. 23-26 substrate sub at [0375] and [0380]-[0383] and [0411]) comprising a display area (FIG. 22 display region AA, [0361]-[0366]) in which emission areas are arranged (FIGS. 16, 17E, 23 and 24, and [0369]-[0370], pixel circuits 10 in the display region AA , and a non-display area (FIG. 22 non-display region NA, [0361]-[0366]) located around the display area (FIG. 22 non-display region NA, [0361]-[0366]); and a circuit layer on the substrate (FIG. 14, circuit layer 10 at [0265]), wherein the circuit layer comprises: light emitting pixel drivers (FIGS. 2, 5 and 7, the driving pixel circuit 10 of the light emitting element 20 form a matrix at [0071] and [0081]-[0085] and [0094]-[0097]) arranged in the display area along a first direction and a second direction (FIG. 2, describing pixel driving circuits arranged in a matrix at [0071]); first auxiliary lines extending in the first direction (FIGS. 22-26, V12, V14 at [0361]-[0373] and [0395]-[0405] and [0420]-[0421]); second auxiliary lines extending in the second direction (FIGS. 22-26, V11, V13 at [0361]-[0373] and [0395]-[0405] and [0411] and [0420]-[0421]); connection auxiliary electrodes (FIG. 26, via/hole section of electrode in box R2 ) adjacent to crossings between the first auxiliary lines and the second auxiliary lines and spaced apart from the first auxiliary lines (FIG. 26 and via hole spaced away from V14 and [0410]); and auxiliary protrusion electrodes (FIG. 26, R2 at [0395]-[0405] and [0411] and [0420]-[0421]) protruding from the second auxiliary lines (FIG. 26 comes off of V13 line), and electrically connected to the connection auxiliary electrodes through an auxiliary connection hole of auxiliary connection holes (FIG. 26 the hole connecting V13 and V14 and specifically disclosed at [0410] [0395]-[0405] and [0411] and [0420]-[0421]); However, although well known in the art, Li does not explicitly disclose wherein one of the first auxiliary lines bends around a corresponding one of the connection auxiliary electrodes. In the same field of endeavor, Li ‘902 discloses lines that bend around connection electrodes wherein one of the first auxiliary lines bends around a corresponding one of the connection auxiliary electrodes (FIG. 12-14, [0112]-[0125] and DVH2 and VREF12 clearly bending around other connections therein, further commonly known as a means to increase density [0127]) . Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display panel and device of Li to incorporate the bending of various lines as disclosed by Li ‘902 because the references are within the same field of endeavor, namely, display pixel and component structures. The motivation to combine Li ‘902 with the teachings of Li would have been to improve density of the pixels (see Li ‘902 at [0127] and [0138] and [0157]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success. Claims 11-13 rejected under 35 U.S.C. 103 as being unpatentable over Li, US 2024/0006574 A1 (hereinafter “Li”) in view of Sakamaki et al., US 2004/0150653 A1 (hereinafter “Sakamaki”) further in view of Li, US 2024/0155902 A1 (hereinafter “Li ‘902”). Regarding claim 11, Li discloses an electronic device ([0432] electronic device having a display function) comprising: a display device (Li at Abstract and FIG. 27, [0431]-[0432] and display device 100) displaying an image ([0004] capable of displaying in high resolution/definition); wherein the display device comprises: a substrate (FIGS. 23-26 substrate sub at [0375] and [0380]-[0383] and [0411]) comprising a display area (FIG. 22 display region AA, [0361]-[0366]) in which emission areas are arranged (FIGS. 16, 17E, 23 and 24, and [0369]-[0370], pixel circuits 10 in the display region AA , and a non-display area (FIG. 22 non-display region NA, [0361]-[0366]) located around the display area (FIG. 22 non-display region NA, [0361]-[0366]); and a circuit layer on the substrate (FIG. 14, circuit layer 10 at [0265]), wherein the circuit layer comprises: light emitting pixel drivers (FIGS. 2, 5 and 7, the driving pixel circuit 10 of the light emitting element 20 form a matrix at [0071] and [0081]-[0085] and [0094]-[0097]) arranged in the display area along a first direction and a second direction (FIG. 2, describing pixel driving circuits arranged in a matrix at [0071]); data lines transmitting a data signal to the light emitting pixel drivers (FIG. 25, data lines ND and [0396]-[0397]); first auxiliary lines extending in the first direction (FIGS. 22-26, V12, V14 at [0361]-[0373] and [0395]-[0405] and [0420]-[0421]); second auxiliary lines extending in the second direction (FIGS. 22-26, V11, V13 at [0361]-[0373] and [0395]-[0405] and [0411] and [0420]-[0421]); connection auxiliary electrodes (FIG. 26, via/hole section of electrode in box R2 ) adjacent to crossings between the first auxiliary lines and the second auxiliary lines and spaced apart from the first auxiliary lines (FIG. 26 and via hole spaced away from V14 and [0410]); and auxiliary protrusion electrodes (FIG. 26, R2 at [0395]-[0405] and [0411] and [0420]-[0421]) protruding from the second auxiliary lines (FIG. 26 comes off of V13 line), and overlapped with respective ones of the connection auxiliary electrodes in a third direction (FIG. 26 the hole connecting V13 and V14 and specifically disclosed at [0410] [0395]-[0405] and [0411] and [0420]-[0421], the hole being the third direction e.g., z axis). However, although these components are well known in the art, Li does not explicitly disclose a memory storing an application; a processor executing the application and transmitting an image data signal and an input control signal to the display device; and a power supply module supplying power to the display device, and wherein one of the first auxiliary lines bends around a corresponding one of the connection auxiliary electrodes. In the same field of endeavor, Sakamaki discloses a memory storing an application (FIG. 19 at [0133] memory 281); a processor (FIG. 19 processor 260 and image signal processor 230 at [0130]-[0131]) executing the application and transmitting an image data signal and an input control signal to the display device (FIG. 19 and [0130]-[0135]); and a power supply module supplying power to the display device (FIG. 19, and power supply 270 at [0131] and [055] with Vcc and Vss at FIG. 8). Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display panel and device of Li to incorporate the various components of a display device as disclosed by Sakamaki because the references are within the same field of endeavor, namely, displays, display driving schemes and display methods. The motivation to combine the architecture and well-known components of Sakamaki with the teachings of Li would have been to improve power consumption and properly function as a display device (see Sakamaki at Abstract). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success. However, although well known in the art, Li in view of Sakamaki does not explicitly disclose wherein one of the first auxiliary lines bends around a corresponding one of the connection auxiliary electrodes. In the same field of endeavor, Li ‘902 discloses lines that bend around connection electrodes wherein one of the first auxiliary lines bends around a corresponding one of the connection auxiliary electrodes (FIG. 12-14, [0112]-[0125] and DVH2 and VREF12 clearly bending around other connections therein, further commonly known as a means to increase density [0127]) . Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display panel and device of Li in view of Sakamaki to incorporate the bending of various lines as disclosed by Li ‘902 because the references are within the same field of endeavor, namely, display pixel and component structures. The motivation to combine Li ‘902 with the teachings of Li in view of Sakamaki would have been to improve density of the pixels (see Li ‘902 at [0127] and [0138] and [0157]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success. Regarding claim 12, Li in view of Sakamaki further in view of Li ‘902 discloses the electronic device of claim 11 (see above), wherein the auxiliary protrusion electrodes electrically connected to the connection auxiliary electrodes through an auxiliary connection hole of auxiliary connection holes (Li at FIG. 26 the hole connecting V13 and V14 and specifically disclosed at [0410] [0395]-[0405] and [0411] and [0420]-[0421]). Regarding claim 13, Li in view of Sakamaki further in view of Li ‘902 discloses the electronic device of claim 12 (see above), wherein the circuit layer further comprises: data connection electrodes adjacent to crossings between the data lines and the first auxiliary lines (FIG. 23 and V11 connection to ND at [0374]-[0375]), and spaced apart from the first auxiliary lines and the connection auxiliary electrodes (FIGS. 22-23 and V11 connection to ND at [0374]-[0375]); and data protrusion electrodes protruding from the data lines and respectively electrically connected to the data connection electrodes through data connection holes (FIGS. 22-23 Protrusion R1 at [0374-[0375]). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARVESH J. NADKARNI whose telephone number is (571)270-7562. The examiner can normally be reached 8AM-5PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C. Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SARVESH J NADKARNI/Examiner, Art Unit 2629
Read full office action

Prosecution Timeline

Mar 03, 2025
Application Filed
Dec 30, 2025
Non-Final Rejection mailed — §103
Feb 27, 2026
Response Filed
Jun 03, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
86%
With Interview (+14.1%)
2y 11m (~1y 6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 512 resolved cases by this examiner. Grant probability derived from career allowance rate.

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