DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (CN202111474803.7 People’s Republic of China 12/03/2021).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 03/10/2025, 06/16/2025, 10/08/2025, 03/16/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 03/10/2025. These drawings are review and accepted by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-6 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-11 of U.S Patent No. 12,274,175 B2 (‘175). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘175 claims.
US Patent No. 12,274,175 B2
US Patent Application No. 2025/0212693 A1
1. A method for fabricating a semiconductor device, comprising: forming a magnetic tunneling junction (MTJ) stack and a top electrode on a substrate; and trimming the top electrode and the MTJ stack vertically and at a slanted angle to form a MTJ having a wide top and a narrow bottom, wherein a width of a bottom surface of the MTJ is less than a width of a top surface of the MTJ.
2. The method of claim 1, further comprising: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; forming a second IMD layer on the first IMD layer; forming a second metal interconnection in the second IMD layer; forming a bottom electrode on the second metal interconnection; forming a MTJ stack on the bottom electrode; forming the top electrode on the MTJ stack; patterning the top electrode, the MTJ stack, and the bottom electrode to form the MTJ; forming a cap layer on the top electrode; forming a third IMD layer on the cap layer; and forming a third metal interconnection in the third IMD layer for connecting the top electrode and the first metal interconnection.
3. The method of claim 2, wherein the third metal interconnection comprises a L-shape.
4. The method of claim 2, wherein a width of a bottom surface of the bottom electrode is less than a width of a top surface of the bottom electrode.
5. The method of claim 2, wherein a thickness of the cap layer adjacent to the MTJ is less than a thickness of the cap layer adjacent to the top electrode.
6. A semiconductor device, comprising: a first inter-metal dielectric (IMD) layer on a substrate; a first metal interconnection in the first IMD layer; a second metal interconnection on the first metal interconnection; a magnetic tunneling junction (MTJ) on the second metal interconnection, wherein a width of a bottom surface of the MTJ is less than a width of a top surface of the MTJ and the MTJ comprises: a pinned layer on the substrate; a barrier layer on the pinned layer; and a free layer on the barrier layer, wherein a width of a top surface of the free layer is greater than a width of a top surface of the barrier layer; a top electrode on the MTJ; and a third metal interconnection on the top electrode and connecting the top electrode and the first metal interconnection.
7. The semiconductor device of claim 6, further comprising: a second IMD layer on the first IMD layer; the second metal interconnection in the second IMD layer; a bottom electrode on the second metal interconnection; the MTJ on the bottom electrode; a cap layer adjacent to the MTJ; a third IMD layer on the cap layer; and the third metal interconnection in the third IMD layer for connecting the top electrode and the first metal interconnection.
8. The semiconductor device of claim 7, wherein the third metal interconnection comprises a L-shape.
9. The semiconductor device of claim 7, wherein a width of a bottom surface of the bottom electrode is less than a width of a top surface of the bottom electrode.
10. The semiconductor device of claim 7, wherein a width of a bottom surface of the top electrode is less than a width of a top surface of the top electrode.
11. The semiconductor device of claim 7, wherein a thickness of the cap layer adjacent to the MTJ is less than a thickness of the cap layer adjacent to the top electrode.
1. A semiconductor device, comprising: a first inter-metal dielectric (IMD) layer on a substrate; a first metal interconnection in the first IMD layer; a second IMD layer on the first IMD layer; a second metal interconnection in the second IMD layer, wherein the second metal interconnection comprises an indentation; and a magnetic tunneling junction (MTJ) on the second metal interconnection, wherein a width of a bottom surface of the MTJ is less than a width of a top surface of the MTJ.
2. The semiconductor device of claim 1, further comprising: a bottom electrode on the second metal interconnection; the MTJ on the bottom electrode; a top electrode on the MTJ; a cap layer adjacent to the MTJ; a third IMD layer on the cap layer; and a third metal interconnection in the third IMD layer for connecting the top electrode and the first metal interconnection.
3. The semiconductor device of claim 2, wherein the third metal interconnection comprises a L-shape.
4. The semiconductor device of claim 2, wherein a width of a bottom surface of the bottom electrode is less than a width of a top surface of the bottom electrode.
5. The semiconductor device of claim 2, wherein a width of a bottom surface of the top electrode is less than a width of a top surface of the top electrode.
6. The semiconductor device of claim 2, wherein a thickness of the cap layer adjacent to the MTJ is less than a thickness of the cap layer adjacent to the top electrode.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under both 35 U.S.C. 102(a)(1) 1as being anticipated by Hung et al (US 11,469,368 B2 hereinafter “Hung”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification
Regarding in dependent Claim 1, Hung, for example in Figs. 1-11, discloses a semiconductor device (see for example in Figs. 1-11), comprising: a first inter-metal dielectric (IMD) layer (e.g., 24; in Figs. 1-11) on a substrate (e.g., substrate 12; in Figs. 1-11); a first metal interconnection (e.g., metal layer 36; in Figs. 1-11) in the first IMD layer (e.g., 24; in Figs. 1-11); a second IMD layer (e.g., 30; in Figs. 1-11) on the first IMD layer (e.g., 24; in Figs. 1-11); a second metal interconnection in the second IMD layer (e.g., 36; in Figs. 1-11), wherein the second metal interconnection comprises an indentation (see for example in Figs. 1-11); and a magnetic tunneling junction (MTJ) (e.g., MTJ 50; in Figs. 2-5 related in Figs. 1, 6-11) on the second metal interconnection (see for example in Figs. 1-11), wherein a width of a bottom surface of the MTJ (e.g., 38; in Figs. 9-11 related in Figs. 1-8) is less than a width of a top surface of the MTJ (e.g., 68; in Figs. 9-11 related in Figs. 1-8).
Regarding claim 2, Hung, for example in Figs. 1-11, discloses further comprising: a bottom electrode on the second metal interconnection; the MTJ on the bottom electrode (see for example in Figs. 9-11 related in Figs. 1-8, as discussed above); a top electrode on the MTJ (see for example in Figs. 9-11 related in Figs. 1-8, as discussed above); a cap layer adjacent to the MTJ (see for example in Figs. 9-11 related in Figs. 1-8, as discussed above); a third IMD layer on the cap layer (see for example in Figs. 9-11 related in Figs. 1-8, as discussed above); and a third metal interconnection in the third IMD layer for connecting the top electrode and the first metal interconnection (see for example in Figs. 9-11 related in Figs. 1-8, as discussed above).
Regarding claim 3, Hung, for example in Figs. 1-11, discloses wherein the third metal interconnection comprises a L-shape (see for example in Figs. 9-11 related in Figs. 1-8, as discussed above).
Regarding claim 4, Hung, for example in Figs. 1-11, discloses wherein a width of a bottom surface of the bottom electrode is less than a width of a top surface of the bottom electrode (see for example in Figs. 9-11 related in Figs. 1-8, as discussed above).
Regarding claim 5, Hung, for example in Figs. 1-11, discloses wherein a width of a bottom surface of the top electrode is less than a width of a top surface of the top electrode (see for example in Figs. 9-11 related in Figs. 1-8, as discussed above).
Regarding claim 6, Hung, for example in Figs. 1-11, discloses wherein a thickness of the cap layer adjacent to the MTJ is less than a thickness of the cap layer adjacent to the top electrode (see for example in Figs. 9-11 related in Figs. 1-8, as discussed above).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 10/14/2026
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